PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER

• US 20110216876A1
• Filed: 02/28/2011
• Published: 09/08/2011
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyazaki, Aya, Kusunoki, Koji, Miyake, Hiroyuki, Amano, Seiko, Shishido, Hideaki, Toyotaka, Kouhei
• Granted Patent: US 8,442,183 B2
• Time in Patent Office: Days
• US Class Current: 377/75
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H05K 7/02 Arrangements of circuit components or wiring on supporting structure

Abstract

An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Claims

1. A pulse signal output circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor;

a ninth transistor; and

a tenth transistor,

wherein a first terminal of the first transistor, a first terminal of the second transistor, and a first output terminal are electrically connected to one another,

wherein a first terminal of the third transistor, a first terminal of the fourth transistor, and a second output terminal are electrically connected to one another,

wherein a first terminal of the fifth transistor, a first terminal of the sixth transistor, and a first terminal of the seventh transistor are electrically connected to one another,

wherein a gate terminal of the first transistor, a gate terminal of the third transistor, and a second terminal of the seventh transistor are electrically connected to one another,

wherein a gate terminal of the second transistor, a gate terminal of the fourth transistor, a gate terminal of the sixth transistor, a first terminal of the eighth transistor, and a first terminal of the ninth transistor are electrically connected to one another,

wherein a second terminal of the eighth transistor and a first terminal of the tenth transistor are electrically connected to each other,

wherein a ratio W/L of a channel width W to a channel length L of the first transistor and a ratio W/L of a channel width W to a channel length L of the third transistor are each larger than a ratio W/L of a channel width W to a channel length L of the sixth transistor,

wherein a ratio W/L of a channel width W to a channel length L of the fifth transistor is larger than the ratio W/L of the channel width W to the channel length L of the sixth transistor,

wherein the ratio W/L of the channel width W to the channel length L of the fifth transistor is equal to a ratio W/L of a channel width W to a channel length L of the seventh transistor, and

wherein the ratio W/L of the channel width W to the channel length L of the third transistor is larger than a ratio W/L of a channel width W to a channel length L of the fourth transistor.

2. The pulse signal output circuit according to claim 1,

wherein a first clock signal is input to a second terminal of the first transistor and a second terminal of the third transistor,

wherein a second clock signal is input to a gate terminal of the eighth transistor,

wherein a third clock signal is input to a gate terminal of the tenth transistor,

wherein a first potential is supplied to a second terminal of the second transistor, a second terminal of the fourth transistor, a second terminal of the sixth transistor, and a second terminal of the ninth transistor,

wherein a second potential higher than the first potential is supplied to a second terminal of the fifth transistor, a gate terminal of the seventh transistor, and a second terminal of the tenth transistor,

wherein a first pulse signal is input to a gate terminal of the fifth transistor and a gate terminal of the ninth transistor, and

wherein a second pulse signal is output from the first output terminal or the second output terminal.

3. The pulse signal output circuit according to claim 1, further comprising a capacitor,

wherein the capacitor is electrically connected to the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, the first terminal of the eighth transistor, and the first terminal of the ninth transistor.

4. The pulse signal output circuit according to claim 1, further comprising an eleventh transistor,

wherein a first terminal of the eleventh transistor is electrically connected to the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, the first terminal of the eighth transistor, and the first terminal of the ninth transistor, and

wherein a channel width W of the eighth transistor and a channel width W of the tenth transistor are each smaller than a channel width W of the eleventh transistor.

5. The pulse signal output circuit according to claim 4,

wherein a second potential is supplied to the second terminal of the eleventh transistor, and

wherein a third pulse signal is input to a gate terminal of the eleventh transistor.

6. A shift register comprising a plurality of the pulse signal output circuits according to claim 1.

7. An n-stage shift register comprising:

two pulse signal output circuits, each of the two pulse signal output circuits being the pulse signal output circuit according to claim 1; and

n pulse signal output circuits, each of the n pulse signal output circuits comprising an eleventh transistor,

wherein a first terminal of the eleventh transistor is electrically connected to the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, the first terminal of the eighth transistor, and the first terminal of the ninth transistor, and

wherein a channel width W of the eighth transistor and a channel width W of the tenth transistor are each smaller than a channel width W of the eleventh transistor,

wherein a channel width W of the eighth transistor in the pulse signal output circuit according to claim 1 is larger than a channel width W of the eighth transistor in one of the n pulse signal output circuits.

8. An n-stage shift register comprising:

two pulse signal output circuits, each of the two pulse signal output circuits being the pulse signal output circuit according to claim 1; and

n pulse signal output circuits, each of the n pulse signal output circuits comprising an eleventh transistor,

wherein a first terminal of the eleventh transistor is electrically connected to the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, the first terminal of the eighth transistor, and the first terminal of the ninth transistor, and

wherein a channel width W of the eighth transistor and a channel width W of the tenth transistor are each smaller than a channel width W of the eleventh transistor,

wherein a channel width W of the tenth transistor in the pulse signal output circuit according to claim 1 is larger than a channel width W of the tenth transistor in one of the n pulse signal output circuits.

9. The pulse signal output circuit according to claim 1,

wherein any one of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth transistors comprises an oxide semiconductor layer.

10. The shift register according to claim 6,

wherein any one of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth transistors comprises an oxide semiconductor layer.