INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING SAME WITH AN INTERPOSER SUBSTRATE

• US 20110217812A1
• Filed: 05/17/2011
• Published: 09/08/2011
• Est. Priority Date: 02/22/2008
• Status: Abandoned Application

• Current Assignee: Andreas Wolter, Harry Hedler, Roland Irsigler
• Original Assignee: Andreas Wolter, Harry Hedler, Roland Irsigler
• Inventors: Wolter, Andreas, Hedler, Harry, Irsigler, Roland
• Application Number:
  US13/109,825
• Publication Number:
  US 20110217812A1
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19011 including integrated passive components
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Fabricating an integrated circuit device includes providing a semiconductor substrate comprising a first surface and a second surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semiconductor substrate. The fabricating further includes forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip, thinning the semiconductor substrate at the second surface after forming the embedding layer, and forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate. Moreover, an integrated circuit device is described.

Claims

1. A method of fabricating an integrated circuit device, comprising:

providing a semiconductor substrate comprising a first surface and a second surface;

forming a wiring layer on the first surface of the semiconductor substrate;

providing a circuit chip;

arranging the circuit chip on the wiring layer of the semiconductor substrate;

forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip;

thinning the semiconductor substrate at the second surface after forming the embedding layer; and

forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate.

2. The method according to claim 1, wherein the semiconductor substrate is thinned to a thickness of less than 100 μ

m.

3. The method according to claim 1, wherein the conductive via comprises a via hole, the via hole having an aspect ratio of depth to width smaller than 1.

4. The method according to claim 1, wherein forming the conductive via comprises:

forming a recess at the second surface of the semiconductor substrate after thinning the semiconductor substrate, the recess exposing a portion of the wiring layer;

forming an insulation layer on sidewalls of the recess; and

forming a conductive layer in the recess being electrically coupled to the wiring layer.

5. The method according to claim 4, wherein the conductive layer is formed on the insulation layer and on the exposed portion of the wiring layer in a manner that a gap is provided between portions of the conductive layer formed on the insulation layer.

6. The method according to claim 5, wherein the insulation layer is further formed covering the second surface of the semiconductor substrate outside of the recess, and wherein the conductive layer is further formed comprising a portion on the insulation layer outside of the recess.

7. The method according claim 1, wherein forming the conductive via comprises:

forming a recess at the first surface of the semiconductor substrate prior to forming the wiring layer;

forming an insulation layer on sidewalls of the recess; and

forming a conductive layer in the recess, wherein the wiring layer is electrically coupled to the conductive layer, and wherein thinning the semiconductor substrate exposes the conductive layer at the second surface of the semiconductor substrate.

8. The method according to claim 7, wherein the conductive layer is formed on the insulation layer at the sides and a bottom area of the recess in a manner that a gap is provided between the portions of the conductive layer formed on the insulation layer.

9. The method according to claim 7, further comprising:

forming a passivation layer on the second surface of the semiconductor substrate after thinning the semiconductor substrate, the passivation layer providing an opening which exposes the conductive layer; and

forming a metallic layer on the conductive layer.

10. The method according to claim 1, wherein the embedding layer is formed having a planar surface.

11. The method according to claim 1, further comprising:

providing an additional substrate; and

arranging the additional substrate on the embedding layer.

12. The method according to claim 1, wherein the circuit chip is provided comprising a contact bump protruding from a surface of the circuit chip, and wherein arranging the circuit chip on the wiring layer comprises connecting the contact bump of the circuit chip to a contact area of the wiring layer.

13. The method according to claim 1, wherein at least two circuit chips are provided, arranged on the wiring layer of the semiconductor substrate horizontally next to each other and encapsulated by the embedding layer, wherein the circuit chips are electrically coupled to each other by means of the wiring layer.

14. The method according to claim 1, further comprising forming a solder ball on the conductive via at the second surface of the semiconductor substrate.