METHOD FOR FORMING INTERCONNECT STRUCTURE HAVING AIRGAP

• US 20110217838A1
• Filed: 03/05/2010
• Published: 09/08/2011
• Est. Priority Date: 03/05/2010
• Status: Active Grant

• Current Assignee: ASM Japan K.K. (ASM International NV)
• Original Assignee: ASM Japan K.K. (ASM International NV)
• Inventors: Kobayashi, Nobuyoshi, Hsieh, Julian J., Fukazawa, Atsuki, Shimizu, Akira, Matsushita, Kiyohiro
• Granted Patent: US 8,241,991 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming an interconnect structure with airgaps, includes: providing a structure having a trench formed on a substrate; depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers by plasma enhanced atomic layer deposition; filling the trench having the sidewall spacers with copper; removing the sidewall spacers to form an airgap structure; and encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench.

Claims

1. A method for forming an interconnect structure with airgaps, comprising:

providing a structure having a trench formed on a substrate;

depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers;

filling the trench having the sidewall spacers with copper;

removing the sidewall spacers to form an airgap structure; and

encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench.

2. The method according to claim 1, wherein the spacer oxide layer is deposited by plasma enhanced atomic layer deposition (PEALD).

3. The method according to claim 1, further comprising depositing a SiC_xN_y-based spacer layer, wherein x and y are independently 0 or 1, on the sidewall spacers by atomic layer deposition before filling the trench, wherein airgaps are formed between the SiC_xN_y-based spacer layer and the sidewalls of the trench.

4. The method according to claim 3, further comprising depositing a pore-sealing layer on the sidewalls before depositing the spacer oxide layer, wherein airgaps are formed between the pore-sealing layer and the SiC_xN_y-based spacer layer.

5. The method according to claim 1, wherein the step of providing the structure comprises:

producing a via structure on the substrate;

performing SLAM (simultaneous location and mapping) processing to cover the via structure with a SLAM layer; and

forming a trench by etching part of the SLAM layer,

wherein the method further comprises forming a via by removing a remaining part of the SLAM layer after the SiC-based spacer layer is deposited on the sidewall spacers but before filling the trench with copper wherein the trench and the via are filled with copper.

6. The method according to claim 5, further comprising depositing a SiC_xN_y-based spacer layer, wherein x and y are independently 0 or 1, on the sidewall spacers by atomic layer deposition before forming the via, wherein airgaps are formed between the SiC_xN_y-based spacer layer and the sidewalls of the trench.

7. The method according to claim 6, further comprising depositing a pore-sealing layer on the sidewalls of the trench before depositing the spacer oxide layer, wherein airgaps are formed between the SiC_xN_y-based spacer layer and the pore-sealing layer.

8. The method according to claim 1, wherein the spacer oxide layer is a silicon oxide layer.

9. The method according to claim 1, wherein the structure having the trench on the substrate is a layered structure comprising a diffusion barrier layer, a low-k layer, and a hard mask formed in this layering order on the substrate, wherein the trench penetrates the hard mask, the low-k layer, and the diffusion barrier layer.

10. The method according to claim 9, wherein the step of providing the structure comprises:

forming a photoresist pattern on the hard mask;

depositing an oxide spacer on the photoresist and an area of the hard mask uncovered by the photoresist, by PEALD at a temperature of 400°

C. or lower;

etching the oxide spacer by a thickness of the oxide spacer in a thickness direction, thereby leaving a sidewall portion of the oxide spacer deposited on sidewalls of the photoresist;

etching an area of the hard mask exposed after the etching of the oxide spacer, followed by removing the sidewall portion of the oxide spacer and the photoresist to obtain a patterned hard mask and an exposed portion of the low-k layer;

forming a second photoresist pattern on the exposed portion of the low-k layer and a part of the patterned hard mask;

depositing a second oxide spacer on the second photoresist and an area of the patterned hard mask uncovered by the second photoresist, by PEALD at a temperature of 400°

C. or lower;

etching the second oxide spacer by a thickness of the second spacer in a thickness direction, thereby leaving a sidewall portion of the second oxide spacer deposited on sidewalls of the second photoresist;

etching an area of the patterned hard mask exposed after the etching of the second oxide spacer, followed by removing the sidewall portion of the second oxide spacer and the second photoresist to obtain a second patterned hard mask and an exposed portion of the low-k layer; and

etching the low-k layer and the diffusion barrier layer using the second patterned hard mask.

11. The method according to claim 9, wherein the step of providing the structure comprises:

forming a photoresist pattern on the hard mask;

trimming the photoresist to reduce the dimensions;

depositing an oxide spacer on the trimmed photoresist and an area of the hard mask uncovered by the trimmed photoresist, by PEALD at a temperature of 400°

C. or lower;

etching the oxide spacer by a thickness of the oxide spacer in a thickness direction, thereby leaving a sidewall portion of the oxide spacer deposited on sidewalls of the trimmed photoresist, followed by removing the trimmed photoresist;

etching an area of the hard mask exposed after the etching of the oxide spacer and the removal of the trimmed photoresist, followed by etching the sidewall portion of the oxide spacer to obtain a patterned hard mask and an exposed portion of the low-k layer; and

etching the low-k layer and the diffusion barrier layer using the patterned hard mask.

12. The method according to claim 3, wherein the SiC_xN_y-based spacer layer on the sidewall spacers is constituted by SiCN.

13. The method according to claim 4, wherein the structure having the trench on the substrate is a layered structure comprising a diffusion barrier layer, a low-k layer, and a hard mask formed in this layering order on the substrate, wherein the trench penetrates the hard mask and the low-k layer, but does not penetrate the diffusion barrier layer, whereby the pore-sealing layer is disposed on the sidewalls of the hard mask and the low-k layer, followed by extending the trench downward to penetrate the diffusion barrier layer before depositing the spacer oxide layer.

14. The method according to claim 5, wherein the via structure is a layered structure comprising a diffusion barrier layer, a low-k layer, and a hard mask in this layering order on the substrate, wherein a via penetrates the hard mask and the low-k layer, but not the diffusion barrier layer, wherein when the via is formed by removing the remaining part of the SLAM layer, the diffusion barrier layer is also removed.

15. The method according to claim 5, wherein the via structure is a layered structure comprising a diffusion barrier layer, a dense low-k layer, a porous low-k layer, and a hard mask in this layering order on the substrate, wherein a via penetrates the hard mask, the porous low-k layer, and the dense low-k layer, wherein the step of forming the trench comprises etching the porous low-k layer, but not the dense low-k layer, wherein when the via is formed by removing the remaining part of the SLAM layer, the diffusion barrier layer is also removed.

16. The method according to claim 1, further comprising selecting a thickness of the spacer oxide layer to achieve a targeted dielectric constant of the encapsulated airgap structure between the copper filled in the trench and copper filled in an immediately adjacent trench, and the step of depositing the spacer oxide layer is controlled to obtain the spacer oxide layer at the selected thickness.

17. The method according to claim 16, wherein the thickness of the spacer oxide layer is controlled at 0.4 nm to 10 nm.

18. The method according to claim 16, wherein the targeted dielectric constant of the encapsulated airgap structure is less than 2.5.