Adaptive-Allocation Of I/O Bandwidth Using A Configurable Interconnect Topology

• US 20110219162A1
• Filed: 05/18/2011
• Published: 09/08/2011
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ching, Michael, Woo, Steven
• Granted Patent: US 8,149,874 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/143 for modulated signals H04L5/1469 takes precedence
• CPC Class Codes: H04L 5/18 Automatic changing of the traffic direction
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Claims

1. An integrated circuit comprising:

an interface having a plurality of contacts including a first set of contacts, a second set of contacts and a third set of contacts; and

control logic, coupled to the interface, to configure the first set of contacts to transmit, the second set of contacts to receive and the third set of contacts to transmit and receive.

2. The integrated circuit of claim 1, wherein the control logic configures the first set of contacts to transmit a first number of parallel signals and the second set of contacts to receive a second number of parallel signals while the third set of contacts either transmit or receive a third number of parallel signals.

3. The integrated circuit of claim 1, wherein the integrated circuit is operable in a mode of operation in which the first set of contacts only transmit, the second set of contacts only receive and the third set of contacts both transmit and receive.

4. The integrated circuit of claim 1, wherein the integrated circuit is operable in a first and second mode of operation,

during the first mode of operation, the number of contacts in each of the first, second and third sets of contacts are predetermined numbers;

and

during the second mode of operation, at least one of the number of contacts in the first, second and third sets of contacts is altered from the predetermined number.

5. The integrated circuit of claim 1, wherein the interface includes a fourth set of contacts and the control logic configures the fourth set of contacts to be disabled.

6. The integrated circuit of claim 1, wherein the interface includes at least one of a transmitter or a receiver coupled to a respective one of the plurality of contacts, the transmitter or receiver to convey corresponding signals in one direction, either away from or to the plurality of contacts.

7. The integrated circuit of claim 1, wherein the interface includes a plurality of transceivers coupled to the plurality of contacts, the plurality of transceivers to output and receive corresponding signals.

8. The integrated circuit of claim 7, wherein the control logic configures the first, second and third sets of contacts in response to a control signal that indicates a number of times at least one of the transceivers in the plurality of transceivers transitions between transmitting and receiving data.

9. An integrated circuit comprising:

an external interface having a plurality of contacts including a first set of contacts, a second set of contacts and a third set of contacts; and

control logic, coupled to the interface, to configure the first set of contacts to transmit, the second set of contacts to receive and the third set of contacts to transmit and receive, the first, second and third sets of contacts are configured in response to a control signal,

wherein the first set of contacts output a first number of parallel signals while the second set of contacts receive a second number of parallel signals,

wherein the third set of contacts either selectively transmit or receive a third number of parallel signals while both the first set of contacts output the first number of parallel signals and the second set of contacts receive the second number of parallel signals.

10. The integrated circuit of claim 9, wherein the integrated circuit is operable in a mode of operation in which the first set of contacts only transmit and the second set of contacts only receive.

11. The integrated circuit of claim 9, wherein the number of contacts in each of the first, second and third sets of contacts are predetermined numbers during initialization;

and

at least one of the number of contacts in the first, second and third sets of contacts is altered from the predetermined number in response to the control signal.

12. The integrated circuit of claim 9, wherein the external interface includes a fourth set of contacts and the control logic configures the fourth set of contacts to be disabled in response to the control signal.

13. The integrated circuit of claim 9, wherein the external interface includes at least one of a transmitter or a receiver coupled to a respective one of the plurality of contacts, the transmitter or receiver to convey corresponding signals in one direction, either away from or to the plurality of contacts.

14. The integrated circuit of claim 9, wherein the external interface includes a plurality of transceivers coupled to the plurality of contacts, the plurality of transceivers to output and receive corresponding signals to and from an external circuit.

15. The integrated circuit of claim 14, wherein the control signal indicates a number of times at least one of the transceivers in the plurality of transceivers transitions between transmitting and receiving data.

16. An integrated circuit comprising:

an interface having a plurality of contacts including a first set of contacts, a second set of contacts, a third set of contacts and a fourth set of contacts; and

control logic, coupled to the interface, to configure the first set of contacts to transmit a first number of parallel signals, the second set of contacts to receive a second number of parallel signals, the third set of contacts to transmit and receive a third number of parallel signals and the fourth set of contacts to be disabled,

wherein the control logic alters at least one of the first, second, third and fourth numbers in response to a control signal.

17. The integrated circuit of claim 16, wherein the control logic alters the first, second, third and fourth numbers in response to the control signal.

18. The integrated circuit of claim 16, wherein the interface includes a plurality of transceivers coupled to the plurality of contacts, the plurality of transceivers to output and receive corresponding signals.

19. The integrated circuit of claim 18, wherein the control signal indicates a number of times at least one of the transceivers in the plurality of transceivers transitions between transmitting and receiving data.

20. The integrated circuit of claim 16, wherein the control logic alters the fourth number in response to a maintenance mode of operation.

21. The integrated circuit of claim 16, wherein the control logic alters the fourth number and wherein the control signal indicates at least one of a phase calibration mode of operation, an impedance calibration mode of operation, a power constrain and a hardware failure.