Method and Apparatus for Optimizing the Performance of a Storage System

• US 20110219170A1
• Filed: 03/05/2010
• Published: 09/08/2011
• Est. Priority Date: 03/05/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: Texas Memory Systems Incorporated (International Business Machines Corporation)
• Inventors: Scheel, Daniel E., Frost, Holloway H.
• Granted Patent: US 8,756,387 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/154 Networked environment
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/261 Storage comprising a plurality of storage devices
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device

Abstract

Methods and apparatuses for optimizing the performance of a storage system comprise a FLASH storage system, a hard drive storage system, and a storage controller. The storage controller is adapted to receive READ and WRITE requests from an external host, and is coupled to the FLASH storage system and the hard drive storage system. The storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address, and provides an alternative WRITE request, including the selected alternative address and the data received in the WRITE request, to the hard drive storage system, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system.

Claims

1. A storage system for processing READ and WRITE requests from an external host, the storage system comprising:

(A) a FLASH storage system;

(B) a hard drive storage system; and

(C) a storage controller adapted to receive READ and WRITE requests from an external host, the storage controller being coupled to the FLASH storage system and the hard drive storage system such that the storage controller can issue READ and WRITE requests to both the FLASH storage system and the hard drive storage system, wherein the storage controller is adapted to;

(i) receive a WRITE request from an external host, the WRITE request containing data and an address corresponding to a location where such data is to be stored and;

(a) forward the received WRITE request to the FLASH storage system;

(b) associate the address provided in the WRITE request with a selected alternative address, and provide an alternative WRITE request to the hard drive storage system wherein the alternative WRITE request includes the selected alternative address and the data received in the WRITE request, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system; and

(ii) receive a READ request from an external host, the READ request containing an address corresponding to a location from which data is to be read and;

(a) forward the received READ request to the FLASH storage system;

(b) return the data received from the FLASH storage system to the external host in the absence of a READ error from the FLASH storage system;

or

(c) issue an alternative READ request to the hard drive storage system, the alternative READ request containing an address corresponding to an alternative address associated by the storage controller with the address received from the external host in the READ request and returning the data received from the hard drive storage system to the external host in the event of a READ error from the FLASH storage system.

2. The storage system of claim 1 wherein the FLASH storage system comprises SLC FLASH memory.

3. The storage system of claim 1 wherein the controller is further adapted to:

determine whether the address provided with the WRITE request was already associated with data stored in the hard drive storage system at the time that the WRITE request was received and,

if the determination indicates that the provided address was already associated with data stored in the hard drive storage system, provide an indication that the data stored is no longer valid data.

4. The storage system of claim 1 wherein the hard drive storage system is adapted to store data across the disc array in a striped manner

5. The storage system of claim 1 wherein the storage controller comprises a programmed microprocessor within a server.

6. The storage system of claim 1 wherein the storage controller is adapted to compact the data stored in the hard drive storage system during idle time using data obtained from the FLASH storage system.

7. The storage system of claim 1 wherein the storage controller is adapted to issue a WRITE request to the FLASH storage system in the event of a READ error from the FLASH storage system that includes data obtained from the hard drive storage system.

21. The storage system of claim 1 wherein the controller is further adapted to:

determine whether the address provided with the WRITE request was already associated with an alternate address in the hard drive storage system,

if the determination indicates that the address provided with the WRITE request was already associated with an alternate address in the hard drive storage system, provide an indication that the alternate address is no longer valid and associate the address provided with the WRITE request with a next sequential alternate address in hard drive storage system.

22. The storage system of claim 1 wherein the controller is further adapted to:

determine whether the address provided with the WRITE request was already associated with an alternate address in the hard drive storage system,

if the determination indicates that the address provided with the WRITE request was already associated with an alternate address in the hard drive storage system, then;

provide an indication that the data stored at the alternate address is no longer valid,

write the data provided with the WRITE request to a next sequential alternate address in the hard drive storage system and associate the address provided with the WRITE request with the next sequential alternate address in hard drive storage system, and

move data that was stored at the next sequential alternate address in the hard drive storage system to another alternate address in the hard drive storage system.

8. A system comprising:

MLC FLASH memory, the MLC FLASH memory providing a given physical MLC FLASH storage space;

a hard drive storage, the hard drive storage providing a given physical storage space that is larger than the physical MLC FLASH storage space; and

a storage controller coupled to the MLC FLASH memory and the hard drive storage, the storage controller being adapted to receive a WRITE request from an external host that contains data and an address where such data is to be stored, the storage controller being further adapted to write the data provided in the WRITE request to a physical location within the MLC FLASH memory and to a physical location within the hard drive storage,

wherein the storage controller is further adapted to receive a READ request from an external host that contains an address from which data is to be read, the storage controller being further adapted to access a physical location within the MLC FLASH memory corresponding to the address received in the READ request and to provide data stored at that address to the external host in the absence of a READ error from the MLC FLASH memory, and to access a physical location within the hard drive storage and to provide data stored at that address to the host in the presence of a READ error from the MLC FLASH memory.

9. The system of claim 8 wherein the storage controller is adapted to associate each address received in a WRITE request from an external host with a physical location within the hard drive storage, wherein the storage controller selects the associated addresses such that the majority of the WRITE operations to the hard drive storage are sequential.

10. The system of claim 8 wherein the physical physical storage space provided by the hard drive storage is more than 150% of the physical storage space provided by the MLC FLASH memory.

11. The system of claim 8 wherein the storage controller and the MLC FLASH memory are located within the same physical device.

12. The system of claim 8 wherein storage controller is further adapted to store data protection information in the hard drive storage and wherein the storage controller is adapted to calculate such data protection information using data obtained through issuance of READ operations to the MLC FLASH memory.

13. The system of claim 12 wherein the storage controller is adapted to calculate the data protection information by performing XOR operations on data obtained from the MLC FLASH memory.

14. The system of claim 8 wherein the storage controller is adapted to provide an indication of available storage space to an external host, and wherein the indication of available storage space identifies a storage space that is less than the physical storage space provided by the hard drive storage and less than the physical storage space provided by the MLC FLASH memory.

15. A storage controller comprising:

a first port adapted to receive READ and WRITE commands from an external host;

a second port adapted to provide READ and WRITE commands to a FLASH storage device and to receive data from the FLASH storage device in response to an issued READ command;

a third port adapted to provide READ and WRITE commands to a hard drive storage device and to receive data from the hard drive storage device in response to an issued READ command;

a processor coupled to the first, second, and third ports, wherein the processor is programmed to;

receive a WRITE command containing an address and data through the first port and issue WRITE commands through both the second and the third ports such that the data provided in the WRITE command is provided through the second port and the third port; and

receive a READ command requesting data and issue a preferred READ command through the second port and a secondary READ command through the third port upon the receipt of error data in response to the preferred READ command.

16. The storage controller of claim 15 wherein the processor is a field programmable gate array.

17. The storage controller of claim 15 wherein the first port is a Fibre Channel port.

18. The storage controller of claim 15 wherein the second port is a SCSI port.

19. The storage controller of claim 15 wherein the processor is further configured to associate a selected address with an address received in a WRITE command and use the associated address as part of the WRITE command issued through the third port, wherein the associated address is selected to promote the number of sequential WRITE commands issued through the third port.

20. The storage controller of claim 19 further including a memory space associated with the processor, the processor being configured to maintain a table in the memory space that links addresses received in WRITE commands though the first port with the associated addresses provided as part of WRITE commands issued through the third port.