MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION

• US 20110219196A1
• Filed: 05/16/2011
• Published: 09/08/2011
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M.
• Granted Patent: US 8,195,918 B2
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.

Claims

1. A computer system, comprising:

a processing unit operable to perform computing functions;

a system controller coupled to the processing unit;

at least one input device coupled to the processing unit through the system controller;

at least one output device coupled to the processing unit through the system controller;

at least one data storage device coupled to the processing unit through the system controller;

a plurality of memory devices; and

a memory hub comprising;

a processor interface coupled to the processing unit;

a plurality of memory interfaces coupled to the processor interface and to respective ones of the memory devices, a local memory controller coupled to each of the plurality of memory through a memory interface comprising;

a cache memory;

a prediction unit configured to predict a memory address of a memory location to access based on memory addresses of previously accessed memory locations; and

an interface memory controller coupled to the prediction unit and configured to receive the predicted memory address, the interface memory controller further configured to generate command and address signals for accessing the memory location in the respective memory corresponding to the predicted memory address in response to receiving the predicted memory address.

2. The computer system of claim 1, wherein the plurality of memory interfaces further comprise a cache and wherein the memory controller is structured to store the data read from the predicted address in the cache.

3. The computer system of claim 1 wherein the memory hub is physically included in the system controller.

4. The computer system of claim 1 wherein the plurality of memory devices are physically packaged in a memory module, and wherein the memory hub is physically included in the memory module.

5. The computer system of claim 1 wherein each of the memory interfaces operates at the same clock speed.

6. The computer system of claim 1 wherein each of the memory devices comprises a dynamic random access memory device.