SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20110220891A1
• Filed: 03/03/2011
• Published: 09/15/2011
• Est. Priority Date: 03/12/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: FUJII, Teruyuki, IMAHAYASHI, Ryota
• Granted Patent: US 9,917,109 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.

Claims

1. A semiconductor device comprising:

an insulating layer;

a wiring embedded in the insulating layer;

an oxide semiconductor layer over the insulating layer;

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

a gate electrode provided to overlap with the oxide semiconductor layer; and

a gate insulating layer provided between the oxide semiconductor layer and the gate electrode,

wherein at least a part of a top surface of the wiring is projected from the insulating layer,

wherein the part of the top surface of the wiring is positioned higher than a part of a surface of the insulating layer,

wherein the wiring in a region projected from the insulating layer is electrically connected to the source electrode or the drain electrode.

2. The semiconductor device according to claim 1,

wherein a part of a side surface of the wiring is exposed.

3. A semiconductor device comprising:

an insulating layer;

a wiring embedded in the insulating layer;

an oxide semiconductor layer over the insulating layer;

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

a gate electrode provided to overlap with the oxide semiconductor layer; and

a gate insulating layer provided between the oxide semiconductor layer and the gate electrode,

wherein the insulating layer is formed so that at least a part of a top surface of the wiring is exposed,

wherein the part of the top surface of the wiring is positioned higher than a part of a surface of the insulating layer,

wherein the wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode, and

wherein a root-mean-square roughness of a region which is a part of the surface of the insulating layer and is in contact with the oxide semiconductor layer is less than or equal to 1 nm.

4. The semiconductor device according to claim 3,

wherein a part of a side surface of the wiring is exposed.

5. A semiconductor device comprising:

an insulating layer;

a wiring embedded in the insulating layer;

an oxide semiconductor layer over the insulating layer;

a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

a gate electrode provided to overlap with the oxide semiconductor layer; and

a gate insulating layer provided between the oxide semiconductor layer and the gate electrode,

wherein the insulating layer is formed so that at least a part of a top surface of the wiring is exposed,

wherein the part of the top surface of the wiring is positioned higher than a part of a surface of the insulating layer,

wherein the wiring in a region exposed from the insulating layer is electrically connected to the gate electrode, and

wherein a root-mean-square roughness of a region which is a part of the surface of the insulating layer and is in contact with the oxide semiconductor layer is less than or equal to 1 nm.

6. The semiconductor device according to claim 5,

wherein a part of a side surface of the wiring is exposed.

7. A semiconductor device comprising:

a first insulating layer;

a wiring embedded in the first insulating layer;

a second insulating layer over the first insulating layer;

a source electrode and a drain electrode embedded in the second insulating layer;

an oxide semiconductor layer partly in contact with a surface of the second insulating layer, a surface of the source electrode, and a surface of the drain electrode;

a gate insulating layer covering the oxide semiconductor layer; and

a gate electrode provided over the gate insulating layer to overlap with the oxide semiconductor layer,

wherein the first insulating layer is formed so that at least a part of a top surface of the wiring is exposed,

wherein the part of the top surface of the wiring is positioned higher than a part of a surface of the first insulating layer,

wherein the wiring in a region exposed from the first insulating layer is electrically connected to the source electrode or the drain electrode, and

wherein a root-mean-square roughness of a region which is a part of the surface of the second insulating layer and is in contact with the oxide semiconductor layer is less than or equal to 1 nm.

8. The semiconductor device according to claim 7,

wherein a part of a side surface of the wiring is exposed.

9. A semiconductor device comprising:

a first transistor;

an insulating layer provided over the first transistor; and

a second transistor provided over the first transistor with the insulating layer positioned therebetween,

wherein the first transistor comprises;

a first channel formation region;

a first gate insulating layer provided over the first channel formation region;

a first gate electrode provided over the first gate insulating layer to overlap with the first channel formation region; and

a first source electrode and a first drain electrode electrically connected to the first channel formation region,

wherein the second transistor comprises;

a second channel formation region comprising an oxide semiconductor layer;

a second source electrode and a second drain electrode electrically connected to the second channel formation region;

a second gate electrode provided to overlap with the second channel formation region; and

a second gate insulating layer provided between the second channel formation region and the second gate electrode,

wherein the insulating layer is formed over the first transistor so that at least a part of a top surface of the first gate electrode is exposed,

wherein the part of the top surface of the first gate electrode is positioned higher than a part of a surface of the insulating layer,

wherein the first gate electrode in a region exposed from the insulating layer is electrically connected to the second source electrode or the second drain electrode, and

wherein a root-mean-square roughness of a region which is a part of the surface of the insulating layer and is in contact with the second channel formation region is less than or equal to 1 nm.

10. The semiconductor device according to claim 9,

wherein part of a side surface of the first gate electrode is exposed.

11. The semiconductor device according to claim 9,

wherein the first channel formation region and the second channel formation region comprise different semiconductor materials.

12. A semiconductor device comprising:

a first transistor;

a first insulating layer provided over the first transistor; and

a second transistor provided over the first transistor with the first insulating layer positioned therebetween,

wherein the first transistor comprises;

a first channel formation region;

a first gate insulating layer provided over the first channel formation region;

a first gate electrode provided over the first gate insulating layer to overlap with the first channel formation region; and

a first source electrode and a first drain electrode electrically connected to the first channel formation region,

wherein the second transistor comprises;

a second source electrode and a second drain electrode embedded in a second insulating layer;

a second channel formation region which is partly in contact with a surface of the second insulating layer, a surface of the second source electrode, and a surface of the second drain electrode and comprises an oxide semiconductor layer;

a second gate insulating layer covering the second channel formation region; and

a second gate electrode provided over the second gate insulating layer to overlap with the second channel formation region,

wherein the first insulating layer is formed over the first transistor so that at least a part of a top surface of the first gate electrode is exposed,

wherein the part of the top surface of the first gate electrode is positioned higher than a part of a surface of the first insulating layer,

wherein the first gate electrode in a region exposed from the first insulating layer is electrically connected to the second source electrode or the second drain electrode, and

wherein a root-mean-square roughness of a region which is a part of the surface of the second insulating layer and is in contact with the second channel formation region is less than or equal to 1 nm.

13. The semiconductor device according to claim 12,

wherein a part of a side surface of the first gate electrode is exposed.

14. The semiconductor device according to claim 12,

wherein the first channel formation region and the second channel formation region comprise different semiconductor materials.

15. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating layer in which a wiring is embedded;

performing planarization treatment on a surface of the first insulating layer so that the planarized first insulating layer partly comprises a surface with a root-mean-square roughness of less than or equal to 1 nm, at least a part of a top surface of the wiring is exposed, and the part of the top surface of the wiring is positioned higher than a part of the surface of the first insulating layer;

forming a source electrode and a drain electrode over the surfaces of the first insulating layer and the wiring so that the source electrode or the drain electrode is electrically connected to the wiring in a region exposed from the first insulating layer;

forming a second insulating layer so as to cover the source electrode and the drain electrode;

performing planarization treatment on a surface of the second insulating layer so that the planarized second insulating layer partly comprises a surface with a root-mean-square roughness of less than or equal to 1 nm and at least a part of top surfaces of the source electrode and the drain electrode is exposed;

forming an oxide semiconductor layer partly in contact with the surface of the planarized second insulating layer, a surface of the source electrode, and a surface of the drain electrode;

forming a gate insulating layer covering the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer so as to overlap with the oxide semiconductor layer.

16. The method for manufacturing a semiconductor device, according to claim 15,

wherein the planarization treatment is performed by CMP treatment.

17. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first transistor comprising a first channel formation region, a first gate insulating layer over the first channel formation region, a first gate electrode which is over the first gate insulating layer and overlaps with the first channel formation region, and a first source electrode and a first drain electrode electrically connected to the first channel formation region;

forming a first insulating layer so as to cover the first transistor;

performing planarization treatment on a surface of the first insulating layer so that the planarized first insulating layer partly comprises a surface with a root-mean-square roughness of less than or equal to 1 nm, at least a part of a top surface of the first gate electrode is exposed, and the part of the top surface of the first gate electrode is positioned higher than a part of the surface of the first insulating layer;

forming a second source electrode and a second drain electrode over the surfaces of the first insulating layer and the first gate electrode so that the second source electrode or the second drain electrode is electrically connected to the first gate electrode in a region exposed from the first insulating layer;

forming a second insulating layer so as to cover the second source electrode and the second drain electrode;

performing planarization treatment on a surface of the second insulating layer so that the planarized second insulating layer partly comprises a surface with a root-mean-square roughness of less than or equal to 1 nm and at least a part of top surfaces of the second source electrode and the second drain electrode is exposed;

forming a second channel formation region which is partly in contact with the surface of the planarized second insulating layer, a surface of the second source electrode, and a surface of the second drain electrode and comprises an oxide semiconductor layer;

forming a second gate insulating layer covering the second channel formation region; and

forming a second gate electrode over the second gate insulating layer so as to overlap with the second channel formation region.

18. The method for manufacturing a semiconductor device, according to claim 17,

wherein the planarization treatment is performed by CMP treatment.