SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
First Claim
1. A semiconductor memory device comprising:
- a base including a substrate and a peripheral circuit formed on a surface of the substrate;
a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base;
a memory film provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers and including a charge storage film;
a channel body provided on an inside of the memory film in the memory hole;
an interconnection provided below the stacked body, and electrically connecting the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region having the memory film and the channel body and the peripheral circuit; and
a contact plug piercing the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.
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Accused Products
Abstract
According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.
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Citations
16 Claims
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1. A semiconductor memory device comprising:
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a base including a substrate and a peripheral circuit formed on a surface of the substrate; a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base; a memory film provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers and including a charge storage film; a channel body provided on an inside of the memory film in the memory hole; an interconnection provided below the stacked body, and electrically connecting the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region having the memory film and the channel body and the peripheral circuit; and a contact plug piercing the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for manufacturing a semiconductor memory device comprising:
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forming a peripheral circuit on a surface of a substrate; stacking alternately a plurality of conductive layers and a plurality of insulating layers above the substrate to form a stacked body; forming a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers; forming a memory film including a charge storage film on an inner wall of the memory hole; forming a channel body on an inside of the memory film in the memory hole; patterning the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region in which the memory film and the channel body are provided, to form a pad; forming an interconnection connecting the peripheral circuit and the pad below the stacked body; forming a contact hole punched through the stacked body in the interconnection region to reach the pad; and providing a contact plug in the contact hole. - View Dependent Claims (14, 15, 16)
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Specification