SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT

• US 20110220990A1
• Filed: 03/11/2010
• Published: 09/15/2011
• Est. Priority Date: 03/11/2010
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Kim, Jongoh, Su, Yi, Chen, John, Weng, Limin, Li, Wenjun, Chang, Hong, Chen, Gary
• Granted Patent: US 8,431,457 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

Claims

1. A method for fabricating a semiconductor device, comprising:

a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches;

b) forming a first conductive region in the plurality of trenches;

c) forming an intermediate dielectric region and a termination protection region by applying a second mask;

d) forming a second conductive region in at least some of the trenches;

e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask;

f) disposing a metal layer; and

g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask.

2. The method of claim 1, wherein the source pickup trenches are located in between adjacent active areas.

3. The method of claim 2, wherein the source pickup trench is surrounded by gate runner/termination trenches.

4. The method of claim 1, further comprising forming asymmetric sidewalls in the gate runner/termination trenches.

5. The method of claim 4, wherein forming asymmetric sidewalls includes undercut etching a portion of an oxide layer that is at least in part covered due to application of the second mask.

6. The method of claim 5, wherein the asymmetric sidewalls includes a first sidewall and a second sidewall, and the first sidewall has a thicker oxide layer than the second sidewall, the first sidewall being closer to the termination area.

7. The method of claim 4, wherein during formation of the intermediate dielectric region and the termination protection region, the second mask covers the gate runner/termination trenches and the source pickup trenches.

8. The method of claim 7, wherein the gate runner/termination trenches are wider than the active gate trenches and the source pickup trenches.

9. The method of claim 1, wherein step a) further comprises forming a plurality of trench spacers around openings of the plurality of trenches.

10. The method of claim 9, wherein said trench spacers protect a semiconductor mesa area for forming a self-aligned cell contact.

11. The method of claim 9, wherein said trench spacers help protect semiconductor surface while forming a polycide on the second conductive region.

12. The method of claim 1, wherein forming an intermediate dielectric region completely fills the active gate trench, but does not completely fill the gate runner/termination trench or gate pickup trench.

13. The method of claim 1, wherein b) includes partially filling the trenches with a conductive material by a first deposition process, partially etching the conductive material, and filling an unfilled portion of the trenches by a second deposition process.

14. The method of claim 13 wherein the plurality of trenches includes one or more high aspect ratio trenches characterized by an aspect ratio of about 10:

1 or greater.

15. A semiconductor device comprising:

a semiconductor layer;

a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom of the trenches and a second conductive region is located at a top of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;

a first electrical contact to the second conductive regions;

a second electrical contact to the first conductive region of the source pickup trenches located in the termination area; and

a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact.

16. The semiconductor device of claim 15 wherein the source pickup trench is located between two adjacent active areas.

17. The semiconductor device of claim 16, wherein the source pickup trench is surrounded by gate runner/termination trenches.

18. The semiconductor device of claim 15 wherein the gate runner/termination trench is asymmetrical, wherein the oxide on a first sidewall of the gate runner/termination trench is thicker than the oxide on the second sidewall of the gate runner/termination trench, the first sidewall being closer to the termination area.

19. The semiconductor device of claim 15 wherein the gate runner/termination trenches are wider than the active area trenches and the source pickup trenches.

20. The semiconductor device of claim 15 wherein the top of the first conductive region is etched back deeply throughout the device and the second electrical contact is a deep contact to the first conductive region.

21. The semiconductor device of claim 15 further comprising a gate pickup trench extending from the gate runner/termination trenches, wherein the oxide around the second conductive region in the gate pickup trench is thicker than the oxide at the bottom of the gate pickup trench.

22. A method of filling trenches with conductive material comprising:

partially filling the trenches with a conductive material by a first deposition process;

partially etching the conductive material; and

filling an unfilled portion of the trenches by a second deposition process.

23. The method of claim 22, wherein the conductive material is polysilicon.

24. The method of claim 23, wherein the trenches have an aspect ratio of 10:

1 or higher.

25. The method of claim 22, wherein the second deposition process deposits the same material as the first deposition process.