Method of Forming a DRAM Array of Devices with Vertically Integrated Recessed Access Device and Digitline

• US 20110220994A1
• Filed: 03/10/2010
• Published: 09/15/2011
• Est. Priority Date: 03/10/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jozwiak, Jim, Tran, Thy, Hwang, David, Parekh, Kunal, Roberts, Ceredig
• Granted Patent: US 8,716,116 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.

Claims

1. A method, comprising:

forming a first trench in a substrate;

forming a second trench in the substrate perpendicular to and in a plane below the first trench;

forming a data line in the second trench;

forming an access line in the first trench, wherein the access line is formed vertically above the data line;

forming a contact vertically above the access line.

2. The method of claim 1, wherein the width of the second trench is less than the width of the first trench.

3. The method of claim 1, wherein forming the data line in the second trench comprises forming a single-sided opening in the trench.

4. The method of claim 3, comprising forming a data line contact in the single-sided opening of the trench, wherein the data line contact electrically connects the substrate to the data line.

5. The method of claim 3, wherein the data lines and the access lines are vertically separated by an insulator disposed on the data line contact.

6. The method of claim 1, wherein forming the access line comprises forming a gate electrode.

7. The method of claim 5, wherein the gate electrode is continuous in the direction of the first trench and discontinuous in the direction of the second trench.

8. The method of claim 6, comprising removing the gate electrode to expose a pillar of the silicon substrate.

9. The method of claim 7, wherein forming a contact comprising patterning a contact region around the pillar and disposing a contract material in the contract region around the pillar.

10. The method of claim 1, wherein the access line comprises a wordline and the data line comprises a digitline.

11. A method of manufacturing a memory device, comprising:

forming a plurality of buried access line trenches in a substrate;

forming a plurality of buried data line trenches in the substrate perpendicular to the first plurality of trenches, wherein the intersection of the first plurality of trenches and the second plurality of trenches define a plurality of pillars extending from the substrate;

forming a plurality of data lines in the second plurality of trenches, wherein the data lines are formed before formation of any transistors of the memory device;

forming a plurality of structures in electrical contact with a top portion of the plurality of pillars.

12. The method of claim 11, comprising forming a plurality of access lines in the first plurality of buried access line trenches after forming the plurality of data lines.

13. The method of claim 11, wherein forming the plurality of structures comprising forming a plurality of contacts.

14. The method of claim 11, wherein forming a plurality of data lines comprises depositing a conductive material in the second plurality of data line trenches and removing a portion of the conductive material to a first depth in the plurality of data line trenches.

15. The method of claim 11, comprising forming a plurality of data line contacts in the plurality of data line trenches.

16. The method of claim 15, wherein forming a plurality of data line contacts comprises:

forming a single-sided opening in each of the plurality of data line trenches; and

exposing a portion of the substrate on a sidewall of each of the plurality of data line trenches;

depositing a polysilicon material between each of the plurality of data lines and the exposed portion of the substrate.

17. The method of claim 11, comprising forming a gate electrode on the plurality of access line trenches and the plurality of data line trenches.

18. The method of claim 17, comprising removing a portion of the gate electrode to expose a top portion of each of the plurality of pillars.

19. The method of claim 17, wherein removing a portion of the gate electrode comprises forming a discontinuous gap in the gate electrode between each pillar in the direction of the plurality of data line trenches.

20. The method of claim 12, wherein the plurality of access lines comprise a plurality of word lines and the plurality of data lines comprise a plurality of digitlines.

21. A memory device, comprising:

a plurality of vertical cell contacts electrically coupled to a silicon substrate;

a plurality of access lines formed in a first direction in a first plane below the vertical cell contacts in the silicon substrate; and

a plurality of data lines formed in a second direction in a second plane below the plurality of access lines in the silicon substrate, wherein the first direction is perpendicular to the second direction.

22. The memory device of claim 21, comprising a plurality of silicon pillars extending vertically from the substrate and defined by an intersection of a first plurality of trenches in the first direction and a second plurality of trenches in the second direction, wherein the plurality of vertical cell contacts are coupled to the silicon pillars.

23. The memory device of claim 22, comprising a plurality of data line contacts disposed between the plurality of data lines and a sidewall of the second plurality of trenches.

24. The memory device of claim 22, comprising a gate oxide disposed around each of the plurality of pillars, wherein the gate oxide is continuous in the first direction and discontinuous in the second direction.

25. The memory device of claim 21, wherein the plurality of access lines comprise a plurality of word lines and the plurality of data lines comprise a plurality of digitlines.