MOSFETs WITH REDUCED CONTACT RESISTANCE
First Claim
1. A semiconductor structure comprising:
- at least one transistor located upon and within a semiconductor substrate, said at least one transistor including a gate stack located on an upper surface of the semiconductor substrate and a source region and a drain region located within the semiconductor substrate at the footprint of the gate stack, wherein at least one of said source region and said drain region has a textured surface that includes at least one peak and at least one valley;
a metal semiconductor alloy disposed on at least the textured surface of the at least one source region and the at least one region; and
a conductively filled via contact formed atop the metal semiconductor alloy.
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Accused Products
Abstract
A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor'"'"'s source region and/or the transistor'"'"'s drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.
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Citations
20 Claims
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1. A semiconductor structure comprising:
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at least one transistor located upon and within a semiconductor substrate, said at least one transistor including a gate stack located on an upper surface of the semiconductor substrate and a source region and a drain region located within the semiconductor substrate at the footprint of the gate stack, wherein at least one of said source region and said drain region has a textured surface that includes at least one peak and at least one valley; a metal semiconductor alloy disposed on at least the textured surface of the at least one source region and the at least one region; and a conductively filled via contact formed atop the metal semiconductor alloy. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating a semiconductor structure comprising:
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providing at least one transistor located within and upon a semiconductor substrate, said at least one transistor includes a gate stack located on an upper surface of the semiconductor substrate and a source region and a drain region located within the semiconductor substrate at a footprint of the gate stack, wherein said source region and said drain region have a planar upper surface; texturing at least one of said source region and drain region to include a roughened surface that has at least one peak and at least one valley; forming a metal semiconductor alloy on the textured surface of said at least one of said source region and said drain region; and forming a conductively filled via contact atop the metal semiconductor alloy. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification