MOSFETs WITH REDUCED CONTACT RESISTANCE

• US 20110221003A1
• Filed: 03/09/2010
• Published: 09/15/2011
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Khakifirooz, Ali, Cheng, Kangguo, Doris, Bruce B., Kulkarni, Pranita
• Granted Patent: US 8,450,807 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor'"'"'s source region and/or the transistor'"'"'s drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.

Claims

1. A semiconductor structure comprising:

at least one transistor located upon and within a semiconductor substrate, said at least one transistor including a gate stack located on an upper surface of the semiconductor substrate and a source region and a drain region located within the semiconductor substrate at the footprint of the gate stack, wherein at least one of said source region and said drain region has a textured surface that includes at least one peak and at least one valley;

a metal semiconductor alloy disposed on at least the textured surface of the at least one source region and the at least one region; and

a conductively filled via contact formed atop the metal semiconductor alloy.

2. The semiconductor structure of claim 1 wherein said at least one valley of said textured surface is located on an original planar upper surface of said at least one of said source region and said drain region.

3. The semiconductor structure of claim 1 wherein said at least one valley of said textured surface is located beneath an original planar upper surface of said at least one of said source region and said drain region.

4. The semiconductor structure of claim 1 wherein both said source region and said drain region have said textured surface.

5. The semiconductor structure of claim 1 wherein said textured surface includes a hemispherical grained semiconductor material.

6. The semiconductor structure of claim 5 wherein said hemispherical grained semiconductor material comprises Si, SiGe or germanium.

7. The semiconductor structure of claim 5 wherein said hemispherical grained semiconductor material is comprised of a same semiconductor material as said semiconductor substrate.

8. The semiconductor structure of claim 5 wherein said hemispherical grained semiconductor material is comprised of a different semiconductor material as said semiconductor substrate.

9. The semiconductor structure of claim 5 wherein said hemispherical grained semiconductor material is doped.

10. The semiconductor structure of claim 1 wherein said at least one transistor includes an n-type transistor, a p-type transistor or a combination of an n-type transistor and a p-type transistor wherein said combination of the n-type transistor and p-type transistor are separated by an isolation located within said semiconductor substrate.

11. A method of fabricating a semiconductor structure comprising:

providing at least one transistor located within and upon a semiconductor substrate, said at least one transistor includes a gate stack located on an upper surface of the semiconductor substrate and a source region and a drain region located within the semiconductor substrate at a footprint of the gate stack, wherein said source region and said drain region have a planar upper surface;

texturing at least one of said source region and drain region to include a roughened surface that has at least one peak and at least one valley;

forming a metal semiconductor alloy on the textured surface of said at least one of said source region and said drain region; and

forming a conductively filled via contact atop the metal semiconductor alloy.

12. The method of claim 11 wherein said texturing includes forming a hemispherical grained semiconductor material on the upper planar surface of at least one of the source region and the drain region.

13. The method of claim 12 wherein said hemispherical grained semiconductor material is formed by chemical vapor deposition.

14. The method of claim 12 wherein said hemispherical grained semiconductor material is comprised of a same semiconductor material as said semiconductor substrate.

15. The method of claim 11 wherein said texturing includes forming a hemispherical grained semiconductor material on the upper planar surface of at least one of the source region and the drain region and etching exposed surfaces of at least one of the source region and the drain region utilizing said hemispherical grained semiconductor material as an etch mask.

16. The method of claim 15 wherein said hemispherical grained semiconductor material is formed by chemical vapor deposition.

17. The method of claim 15 wherein said etching includes ammonia.

18. The method of claim 15 wherein said hemispherical grained semiconductor material is comprised of a different semiconductor material as said semiconductor substrate.

19. The method of claim 11 wherein both said source region and said drain region are textured to include said roughened surface.

20. The method of claim 11 wherein said forming said metal semiconductor alloy includes forming a metal layer atop the roughened surface, and annealing.