BIAS CIRCUIT AND METHOD OF MANUFACTURING THE SAME

• US 20110221032A1
• Filed: 12/01/2009
• Published: 09/15/2011
• Est. Priority Date: 12/04/2008
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kishimoto, Shuya, Hamada, Yasuhiro, Maruhashi, Kenichi
• Granted Patent: US 8,975,725 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/255 Amplifier input adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/423 Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
• CPC Class Codes: H03F 3/195 in integrated circuits

Abstract

A bias circuit according to the present invention includes a resistor layer 2 which is placed above a substrate 1 and connected to a ground potential, and a conductor 4 for forming an inductor 5 placed above the resistor layer 2. Further, a manufacturing method of the bias circuit according to the present invention generates the resistor layer 2 above the substrate 1 and is connected to the ground potential, and generates the conductor 4 for forming the inductor 5 above the resistor layer 2. The present invention can provide a bias circuit and a manufacturing method of the bias circuit that enables easy integration on a semiconductor substrate and prevents parasitic oscillation.

Claims

1. A bias circuit comprising:

a resistor layer that is placed over a substrate and connected to a ground potential; and

a conductor that is placed above the resistor layer apart from the resistor layer and forms an inductor.

2. The bias circuit according to claim 1, wherein the conductor for forming the inductor is placed with an insulator interposed therebetween, the insulator being placed above the resistor layer.

3. The bias circuit according to claim 1, wherein an input terminal of the inductor is connected to a power supply, and an output terminal of the inductor is connected to a power supply unit of an integrated circuit.

4. The bias circuit according to claim 1, wherein a gap between the resistor layer and a lower surface of the inductor is 1 μ

m or less.

5. The bias circuit according to claim 1, wherein a wire of the inductor is formed by interlayer-connecting metal wires of a plurality of layers formed inside the insulator by a via.

6. The bias circuit according to claim 1, wherein the wire of the inductor is formed by interlayer-connecting a polysilicon layer and metal wires of a plurality of layers by the via.

7. The bias circuit according to claim 1, wherein the wire of the inductor is formed of gold.

8. The bias circuit according to claim 1, wherein the inductor is placed below a pad layer which supplies bias and is connected to the pad layer by the via.

9. The bias circuit according to claim 1, wherein the substrate is silicon.

10. The bias circuit according to claim 1, wherein the substrate is a Silicon-on-Insulator substrate.

11. The bias circuit according to claim 1, wherein the substrate is a compound semiconductor.

12. The bias circuit according to claim 1, wherein the substrate is ceramic.

13. The bias circuit according to claim 1, wherein the resistor layer is formed in a silicon IC process.

14. The bias circuit according to claim 1, wherein the resistor layer is a thin metal film resistor.

15. The bias circuit according to claim 1, wherein the insulator placed above the resistor is silicon nitride.

16. The bias circuit according to claim 1, wherein the insulator placed above the resistor layer is oxide silicon.

17. A manufacturing method of a bias circuit comprising:

generating a resistor layer that is connected to a ground potential over a substrate; and

generating a conductor for forming an inductor above the resistor layer apart from the resistor layer.

18. The manufacturing method of the bias circuit according to claim 17, further comprising generating an insulator between the resistor layer and the conductor for forming the inductor.