PRE-PROCESSING TO REDUCE WAFER LEVEL WARPAGE

• US 20110221053A1
• Filed: 03/11/2010
• Published: 09/15/2011
• Est. Priority Date: 03/11/2010
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Nakamoto, Mark, Chandrasekaran, Arvind
• Application Number:
  US12/688,500
• Publication Number:
  US 20110221053A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A method for packaging a stacked integrated circuit (IC) includes pre-processing the stacked IC before releasing the stacked IC from the carrier wafer. Pre-processing reduces wafer warpage and simplifies the packaging process by dicing materials separately. Pre-processing may be performed on the first tier wafer of a stacked IC during manufacturing to partially or completely dice the first tier wafer into first tier dies before release from the carrier wafer. Pre-processing may also be performed by laser cutting the mold compound surrounding the first tier wafer and second tier dies before releasing the stacked IC from the carrier wafer. Openings in the first tier wafer and/or mold compound allows balancing of stresses in the packaging process and reduction of wafer warpage.

Claims

1. A method for packaging a stacked integrated circuit, the method comprising:

attaching a carrier wafer to a first tier wafer;

coupling a plurality of second tier dies to the first tier wafer to form a group of stacked integrated circuits after attaching the carrier wafer to the first tier wafer;

applying a mold compound to the plurality of second tier dies coupled to the first tier wafer after coupling the plurality of second tier dies to the first tier wafer,

pre-processing the group of stacked integrated circuits; and

releasing the first tier wafer from the carrier wafer after pre-processing the group of stacked integrated circuits.

2. The method of claim 1, in which pre-processing is performed after coupling the plurality of second tier dies to the first tier wafer.

3. The method of claim 2, in which pre-processing comprises partially dicing the first tier wafer into a plurality of first tier dies.

4. The method of claim 2, in which pre-processing comprises fully dicing the first tier wafer into a plurality of first tier dies.

5. The method of claim 1, in which pre-processing is performed before coupling the plurality of second tier dies to the first tier wafer.

6. The method of claim 5, in which pre-processing comprises wafer-level etching of the first tier wafer into a plurality of first tier dies.

7. The method of claim 1, in which pre-processing is performed after applying the mold compound.

8. The method of claim 7, in which pre-processing comprises laser cutting the mold compound.

9. The method of claim 1, further comprising dicing the mold compound after releasing the first tier wafer from the carrier wafer.

10. The method of claim 1, further comprising:

performing backside processing after mounting the first tier wafer on the carrier wafer; and

performing back-end assembly after dicing the mold compound.

11. The method of claim 1, further comprising integrating the stacked integrated circuit into at least one of a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

12. An integrated circuit, comprising:

a plurality of first tier dies stacked on a carrier wafer, the plurality of first tier dies at least partially separated;

a plurality of second tier dies stacked on the plurality of first tier dies; and

a mold compound surrounding the plurality of first tier dies and surrounding the plurality of second tier dies, the mold compound filling spaces between the plurality of first tier dies.

13. The integrated circuit of claim 12, in which the plurality of first tier dies are completely separated.

14. The integrated circuit of claim 12, in which the integrated circuit is integrated into at least one of a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

15. A method for packaging a stacked integrated circuit, the method comprising the steps of:

attaching a carrier wafer to a first tier wafer;

coupling a plurality of second tier dies to the first tier wafer to form a group of stacked integrated circuits after attaching the carrier wafer to the first tier wafer;

pre-processing the group of stacked integrated circuits; and

releasing the first tier wafer from the carrier wafer after pre-processing the group of stacked integrated circuits.

16. The method of claim 15, further comprising integrating the stacked integrated circuit into at least one of a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

17. A stacked integrated circuit manufactured by a process, comprising:

attaching a carrier wafer to a first tier wafer;

coupling a plurality of second tier dies to the first tier wafer to form a group of stacked integrated circuits after attaching the carrier wafer to the first tier wafer;

pre-processing the group of stacked integrated circuits; and

releasing the first tier wafer from the carrier wafer after pre-processing the group of stacked integrated circuits.

18. The stacked integrated circuit of claim 17, in which the stacked integrated circuit is integrated into at least one of a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

19. An integrated circuit, comprising:

a first tier wafer stacked on a carrier wafer, the first tier wafer including means for separating the first tier wafer into a plurality of first tier dies;

a plurality of second tier dies stacked on the first tier wafer; and

a mold compound surrounding the plurality of first tier dies and surrounding the plurality of second tier dies, the mold compound filling the separating means.

20. The integrated circuit of claim 19, in which the integrated circuit is integrated into at least one of a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.