Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation

• US 20110221057A1
• Filed: 02/17/2011
• Published: 09/15/2011
• Est. Priority Date: 03/12/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Chen, Kang, Fang, Jianmin, Lin, Yaojian, Feng, Xia
• Granted Patent: US 8,183,095 B2
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer containing a plurality of semiconductor die separated by a saw street;

forming a first insulating layer over the semiconductor wafer;

forming a protective layer over the first insulating layer including an edge of the semiconductor die along the saw street;

singulating the semiconductor wafer through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die;

leading with the protective layer, mounting the semiconductor die to a carrier;

depositing an encapsulant over the semiconductor die and carrier;

removing the carrier and protective layer; and

forming a build-up interconnect structure over the semiconductor die and encapsulant.

2. The method of claim 1, wherein the first insulating layer has a non-planar surface and the protective layer has a planar surface.

3. The method of claim 1, further including removing a portion of the encapsulant opposite the first insulating layer.

4. The method of claim 1, further including forming the protective layer over an entire surface of the semiconductor wafer.

5. The method of claim 1, further including forming an opening in the protective layer over the saw street.

6. The method of claim 1, wherein forming the build-up interconnect structure includes:

forming a second insulating layer over the encapsulant and first insulating layer;

forming a conductive layer over the second insulating layer; and

forming a third insulating layer over the second insulating layer and conductive layer.

7. A method of making a semiconductor device, comprising:

providing a semiconductor wafer containing a plurality of semiconductor die;

forming a first insulating layer over the semiconductor wafer;

forming a protective layer over the first insulating layer;

singulating the semiconductor wafer through the protective layer to separate the semiconductor die while protecting an edge of the semiconductor die;

mounting the semiconductor die to a carrier;

depositing an encapsulant over the semiconductor die and carrier;

removing the carrier and protective layer; and

forming a build-up interconnect structure over the semiconductor die and encapsulant.

8. The method of claim 7, wherein the first insulating layer has a non-planar surface and the protective layer has a planar surface.

9. The method of claim 7, further including removing a portion of the encapsulant opposite the first insulating layer.

10. The method of claim 7, further including forming the protective layer over an entire surface of the semiconductor wafer.

11. The method of claim 7, wherein the protective layer has an opening over the saw street.

12. The method of claim 7, further including forming a cavity in the encapsulant around the semiconductor die.

13. The method of claim 7, further including forming a cavity in the encapsulant prior to removing the protective layer.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first insulating layer over the semiconductor die;

forming a protective layer over the first insulating layer;

leading with the protective layer, mounting the semiconductor die to a carrier;

depositing an encapsulant over the semiconductor die and carrier;

removing the carrier and protective layer; and

forming a build-up interconnect structure over the semiconductor die and encapsulant.

15. The method of claim 14, wherein the first insulating layer has a non-planar surface.

16. The method of claim 14, wherein the protective layer has a planar surface.

17. The method of claim 14, wherein the protective layer protects an edge of the semiconductor die.

18. The method of claim 14, further including:

applying a tape over the encapsulant and protective layer;

removing a portion of the encapsulant opposite the first insulating layer; and

removing the protective layer with the tape.

19. The method of claim 14, further including removing the protective layer with deionized water and rinse or chemical stripping.

20. The method of claim 14, further including forming a cavity in the encapsulant around the semiconductor die.

21. A semiconductor device, comprising:

a semiconductor die;

a first insulating layer formed over the semiconductor die;

a protective layer formed over the first insulating layer;

an encapsulant deposited over the semiconductor die; and

a build-up interconnect structure formed over the semiconductor die and encapsulant.

22. The semiconductor device of claim 21, wherein the first insulating layer has a non-planar surface.

23. The semiconductor device of claim 21, wherein the protective layer has a planar surface.

24. The semiconductor device of claim 21, wherein the protective layer protects an edge of the semiconductor die.

25. The semiconductor device of claim 21, further including a cavity formed in the encapsulant.