Impedence Balancer

• US 20110221398A1
• Filed: 03/15/2010
• Published: 09/15/2011
• Est. Priority Date: 03/15/2010
• Status: Abandoned Application

• Current Assignee: Electronvault, Inc.
• Original Assignee: Electronvault, Inc.
• Inventors: Ferber, Robert R. JR.
• Application Number:
  US12/724,410
• Publication Number:
  US 20110221398A1
• Time in Patent Office: Days
• US Class Current: 320/166
• CPC Class Codes: B60L 2240/547 Voltage
• CPC Class Codes: B60L 58/12 responding to state of charge [SoC]
• CPC Class Codes: B60L 58/15 Preventing overcharging
• CPC Class Codes: B60L 58/22 Balancing the charge of battery modules
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries
• CPC Class Codes: Y02T 10/92 Energy efficient charging or discharging systems for batteries, ultracapacitors, supercapacitors or double-layer capacitors specially adapted for vehicles

Abstract

An impedance balancer for power cell balancing using changes in impedance is provided. The apparatus may include a rail capacitor that is switchably connected to a first capacitor and switchably connected to a second capacitor. The first capacitor may also be switchably connected to a first power cell and the second capacitor may also switchably connected to a second power cell. Via controllable switches, the first and second capacitors may shuttle energy between the power cells through the rail capacitor. Additional and related methods and apparatuses are also provided.

Claims

1. An impedance balancer comprising:

a rail capacitor comprising rail capacitor terminals;

a first capacitor comprising first capacitor terminals, wherein the first capacitor terminals are switchably connected across terminals of a first power cell via a first set of controllable switches, and wherein the first capacitor terminals are also switchably connected across the rail capacitor terminals via a second set of controllable switches; and

a second capacitor comprising second capacitor terminals, wherein the second capacitor terminals are switchably connected across the rail capacitor terminals via a third set of controllable switches, and wherein the second capacitor terminals are also switchably connected across terminals of a second power cell via a fourth set of controllable switches.

2. The impedance balancer of claim 1 further comprising control signal circuitry configured to provide respective control signals to the first, second, third and forth sets of controllable switches.

3. The impedance balancer of claim 1 further comprising voltage monitoring circuitry configured to:

receive an indication of a voltage across the rail capacitor terminals; and

provide a status indicator for an energy system based on the received indication.

4. The impedance balancer of claim 1 further comprising voltage monitoring circuitry configured to:

compare an indication of a voltage across the rail capacitor terminals to an overvoltage reference to determine an overvoltage status of an energy system; and

compare an indication of a voltage across the rail capacitor terminals to an undervoltage reference to determine an undervoltage status of the energy system.

5. The impedance balancer of claim 1, wherein the first power cell is electrically connected in parallel with at least a third power cell, and wherein the second power cell is electrically connected in parallel with at least a fourth power cell.

6. The impedance balancer of claim 1 further comprising control signal circuitry configured to provide respective control signals to each switch within the first and second sets of controllable switches, wherein the respective control signals are configured to:

cause the first set of controllable switches to generate an electrical connection between the first capacitor terminals and the terminals of the first power cell to charge or discharge the first capacitor across the terminals of the first power cell; and

cause the second set of controllable switches to generate an electrical connection between the first capacitor terminals and the rail capacitor terminals to charge or discharge the first capacitor across the terminals of the rail capacitor.

7. The impedance balancer of claim 1 further comprising control signal circuitry configured to provide a first set of control signals to the second set of controllable switches and a second set of control signals to the third set of controllable switches;

wherein the first set of control signals cause the second set of controllable switches to generate and break an electrical connection between the first capacitor terminals and the rail capacitor terminals based on a frequency of the first set of control signals; and

wherein the second set of control signals cause the third set of controllable switches to generate and break an electrical connection between the rail capacitor terminals and the second capacitor terminals based on a frequency of the second set of control signals

8. The impedance balancer of claim 1 further comprising control signal circuitry configured to provide a first set of control signals to the first set of controllable switches and a second set of control signals to the second set of controllable switches, wherein respective frequencies of the first set of control signals and the second set of control signals are based on an output current of an energy system comprising the first power cell and the second power cell.

9. The impedance balancer of claim 1 further comprising control signal circuitry configured to provide respective control signals to each of the switches within the first, second, third, and forth sets of controllable switches, wherein the respective control signals are configured to:

cause the first set of controllable switches to generate an electrical connection between the first capacitor terminals and the terminals of the first power cell to charge or discharge the first capacitor across the terminals of the first power cell;

cause the second set of controllable switches to generate an electrical connection between the first capacitor terminals and the rail capacitor terminals to charge or discharge the first capacitor across the terminals of the rail capacitor;

cause the third set of controllable switches to generate an electrical connection between the rail capacitor terminals and the second capacitor terminals to charge or discharge the second capacitor across the rail capacitor terminals; and

cause the fourth set of controllable switches to generate an electrical connection between the second capacitor terminals and the terminals of the second power cell to charge or discharge the second capacitor across the terminals of the second power cell;

wherein the first and fourth sets of controllable switches do not generate electrical connections simultaneously.

10. The impedance balancer of claim 1 further comprising control signal circuitry configured to provide respective control signals to each of the switches within the first, second, third, and forth sets of controllable switches, wherein the respective control signals are configured to control the second and third sets of controllable switches to prevent the rail capacitor terminals from being electrically connected to the first capacitor terminals and the second capacitor terminals simultaneously.

11. The impedance balancer of claim 1, wherein at least the controllable switches within the first, second, third, and fourth sets of controllable switches is a transistor, and wherein a gate terminal of the transistor is driven by a control signal provided via a terminal of a transformer.

12. The impedance balancer of claim 1, wherein at least the controllable switches within the first, second, third, and fourth sets of controllable switches is a transistor, and wherein a gate terminal of the transistor is driven by a control signal provided via a terminal of a transformer, a waveform of the control signal being modified by a shunt resistor and a diode connected across the secondary terminals of the transformer.

13. A method for performing power cell balancing, the method comprising:

generating an electrical connection between terminals of a first capacitor and terminals of a first power cell to charge or discharge the first capacitor across the terminals of the first power cell;

generating an electrical connection between the terminals of the first capacitor and terminals of a rail capacitor to charge or discharge the first capacitor across the terminals of the rail capacitor;

generating an electrical connection between the terminals of the rail capacitor and terminals of a second capacitor to charge or discharge the second capacitor across the rail capacitor terminals; and

generating an electrical connection between the terminals of the second capacitor and terminals of a second power cell to charge or discharge the second capacitor across terminals of a second power cell.

14. The method of claim 13 further comprising:

receiving control signals at a first set of controllable switches to generate the electrical connection between the terminals of the first capacitor and the terminals of the first power cell;

receiving control signals at a second set of controllable switches to generate the electrical connection between the terminals of the first capacitor and the terminals of a rail capacitor;

receiving control signals at a third set of controllable switches to generate the electrical connection between the terminals of the rail capacitor and the terminals of the second capacitor; and

receiving control signals at a fourth set of controllable switches to generate the electrical connection between the terminals of the second capacitor and the terminals of the second power cell.

15. The method of claim 13 further comprising:

receiving an indication of a voltage across the terminals of the rail capacitor; and

providing a status indicator for an energy system based on the received indication.

16. The method of claim 13 further comprising:

comparing an indication of a voltage across the terminals of the rail capacitor to an overvoltage reference to determine an overvoltage status of an energy system; and

comparing an indication of a voltage across the terminals of the rail terminals to an undervoltage reference to determine an undervoltage status of the energy system.

17. The method of claim 13, wherein the first power cell is electrically connected in parallel with at least a third power cell, and wherein the second power cell is electrically connected in parallel with at least a fourth power cell.

18. The method of claim 13, further comprising:

generating and breaking the electrical connection between the terminals of the first capacitor and terminals of a rail capacitor based on a frequency of a first set of control signals; and

generating and breaking the electrical connection between the terminals of the rail capacitor and the terminals of a second capacitor based on a frequency of a second set of signals;

wherein the first set of control signals and second set of control signal are further configured to prevent the rail capacitor terminals from being electrically connected to the first capacitor terminals and the second capacitor terminals simultaneously.

19. The method of claim 13, further comprising:

generating and breaking the electrical connection between the terminals of the first capacitor and terminals of a rail capacitor based on a frequency of a first set of control signals; and

generating and breaking the electrical connection between the terminals of the rail capacitor and the terminals of a second capacitor based on a frequency of a second set of signals;

wherein respective frequencies of the first set of control signals and the second set of control signals are based on an output current of an energy system comprising the first power cell and the second power cell.

20. The method of claim 13, wherein at least one of generating the electrical connection between the terminals of the first capacitor and the terminals of a first power cell, generating the electrical connection between the terminals of the first capacitor and the terminals of the rail capacitor, generating the electrical connection between the terminals of the rail capacitor and the terminals of the second capacitor, or generating the electrical connection between the terminals of the second capacitor and terminals of the second power cell is performed by driving a gate terminal of a transistor via a terminal of a transformer.

21. The method of claim 13, wherein at least one of generating the electrical connection between the terminals of the first capacitor and the terminals of a first power cell, generating the electrical connection between the terminals of the first capacitor and the terminals of the rail capacitor, generating the electrical connection between the terminals of the rail capacitor and the terminals of the second capacitor, or generating the electrical connection between the terminals of the second capacitor and terminals of the second power cell is performed by driving a gate terminal of a transistor via a terminal of a transformer, a waveform of a signal provided to the gate terminal being modified by a shunt resistor and a diode connected across the terminals of the transformer.

22. An energy management system monitor comprising circuitry configured to measure a voltage across a rail capacitor and output a status indication based on the measured voltage, wherein the rail capacitor is switchably connected to a first capacitor and switchably connected to a second capacitor, and wherein the first capacitor is also switchably connected to a first power cell and the second capacitor is also switchably connected to a second power cell.

23. The energy management system monitor of claim 22, wherein the circuitry configured to output the status indication includes being configured to output a plurality of status indications by comparing the measured voltage to a respective plurality of reference voltages.