LOGIC CIRCUIT

• US 20110221475A1
• Filed: 05/26/2011
• Published: 09/15/2011
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AKIMOTO, Kengo, KOYAMA, Jun, TSUBUKU, Masashi
• Granted Patent: US 8,373,443 B2
• Time in Patent Office: Days
• US Class Current: 326/120
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 19/09407 of the same canal type
• CPC Class Codes: H03K 19/09421 Diode field-effect transistor logic H03K19/0956, H03K19/096 take precedence
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

Claims

1. A logic circuit comprising:

a first transistor having a gate, a source, and a drain,

a second transistor having a gate, a source, and a drain,

a first terminal electrically connected to the gate of the second transistor; and

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to one of the source and the drain of the first transistor, and the gate of the first transistor is electrically connected to the other of the source and the drain of the first transistor;

wherein one of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, and a low power supply voltage terminal is electrically connected to the other of the source and the drain of the second transistor,

wherein each of the first transistor and the second transistor includes;

a gate electrode;

a gate insulating layer provided over the gate electrode;

a first oxide semiconductor layer provided over the gate insulating layer;

a source region and a drain region in contact with part of the first oxide semiconductor layer, wherein the source region and the drain region are second oxide semiconductor layers;

a source electrode in contact with the source region; and

a drain electrode in contact with the drain region,

wherein the second transistor includes a reduction prevention layer over the first oxide semiconductor layer, the source electrode, and the drain electrode, and

wherein the first transistor does not include a reduction prevention layer over the first oxide semiconductor layer, the source electrode, and the drain electrode.

2. The logic circuit according to claim 1, wherein the second transistor includes an oxygen vacancy control region between the source electrode and the drain electrode over a surface of the first oxide semiconductor layer, which is opposite to a surface in contact with the gate insulating layer.

3. The logic circuit according to claim 1, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layers contains indium, gallium, and zinc.

4. The logic circuit according to claim 1, wherein the first transistor and the second transistor have the same conductivity type.

5. The logic circuit according to claim 1, wherein one of the source electrode and the drain electrode of the second transistor is in contact with the gate electrode of the first transistor through an opening portion provided in the gate insulating layer.

6. A logic circuit comprising:

a first transistor having a gate, a source, and a drain, wherein a first clock signal is input to the gate of the first transistor, and an input signal is input to the one of the source and the drain of the first transistor;

a first inverter having an input terminal and an output terminal, the input terminal of the first inverter electrically connected to the other of the source and the drain of the first transistor;

a second inverter having an input terminal and an output terminal, the input terminal of the second inverter electrically connected to the output terminal of the first inverter;

a third inverter having an input terminal electrically connected to the output terminal of the first inverter, and an output terminal outputting an output signal; and

a second transistor having a gate, a source, and a drain, wherein a second clock signal is input to the gate of the second transistor, one of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to the output terminal of the second inverter,

wherein each of the first inverter and the second inverter includes;

a third transistor having a gate, a source, and a drain,

a fourth transistor having a gate, a source, and a drain,

a first terminal electrically connected to the gate of the fourth transistor;

a second terminal electrically connected to a portion where the fourth transistor is connected to the third transistor,

wherein a high power supply voltage terminal is electrically connected to one of the source and the drain of the third transistor, and the gate of the third transistor is electrically connected to the other of the source and the drain of the third transistor;

wherein one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and a low power supply voltage terminal is electrically connected to the other of the source and the drain of the fourth transistor,

wherein each of the third transistor and the fourth transistor includes;

a gate electrode;

a gate insulating layer provided over the gate electrode;

a first oxide semiconductor layer provided over the gate insulating layer;

a source region and a drain region in contact with part of the first oxide semiconductor layer, wherein the source region and the drain region are second oxide semiconductor layers;

a source electrode in contact with the source region; and

a drain electrode in contact with the drain region,

wherein the fourth transistor includes a reduction prevention layer over the first oxide semiconductor layer, the source electrode, and the drain electrode, and

wherein the third transistor does not include a reduction prevention layer over the first oxide semiconductor layer, the source electrode, and the drain electrode.

7. The logic circuit according to claim 6, wherein the fourth transistor includes an oxygen vacancy control region between the source electrode and the drain electrode over a surface of the first oxide semiconductor layer, which is opposite to a surface in contact with the gate insulating layer.

8. The logic circuit according to claim 6, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layers contains indium, gallium, and zinc.

9. The logic circuit according to claim 6, wherein the third transistor and the fourth transistor have the same conductivity type.

10. The logic circuit according to claim 6, wherein one of the source electrode and the drain electrode of the fourth transistor is in contact with the gate electrode of the third transistor through an opening portion provided in the gate insulating layer.

11. A logic circuit comprising:

a first transistor having a gate, a source, and a drain,

a second transistor having a gate, a source, and a drain,

a first terminal electrically connected to the gate of the second transistor;

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to one of the source and the drain of the first transistor, and the gate of the first transistor is electrically connected to the other of the source and the drain of the first transistor;

wherein one of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, and a low power supply voltage terminal is electrically connected to the other of the source and the drain of the second transistor,

wherein each of the first transistor and the second transistor includes;

a gate electrode;

a gate insulating layer provided over the gate electrode;

an oxide semiconductor layer provided over the gate insulating layer; and

a source electrode and a drain electrode in contact with part of the oxide semiconductor layer,

wherein the second transistor includes a reduction prevention layer over the oxide semiconductor layer, the source electrode, and the drain electrode, and

wherein the first transistor does not include a reduction prevention layer over the oxide semiconductor layer, the source electrode, and the drain electrode.

12. The logic circuit according to claim 11, wherein the second transistor includes an oxygen vacancy control region between the source electrode and the drain electrode over a surface of the oxide semiconductor layer, which is opposite to a surface in contact with the gate insulating layer.

13. The logic circuit according to claim 11, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

14. The logic circuit according to claim 11, wherein the first transistor and the second transistor have the same conductivity type.

15. The logic circuit according to claim 11, wherein one of the source electrode and the drain electrode of the second transistor is in contact with the gate electrode of the first transistor through an opening portion provided in the gate insulating layer.

16. A logic circuit comprising:

a first transistor having a gate, a source, and a drain, wherein a first clock signal is input to the gate of the first transistor, and an input signal is input to the one of the source and the drain of the first transistor;

a first inverter having an input terminal and an output terminal, the input terminal of the first inverter electrically connected to the other of the source and the drain of the first transistor;

a second inverter having an input terminal and an output terminal, the input terminal of the second inverter electrically connected to the output terminal of the first inverter;

a third inverter having an input terminal electrically connected to the output terminal of the first inverter, and an output terminal outputting an output signal; and

a fourth transistor having a gate, a source, and a drain, wherein a second clock signal is input to the gate of the second transistor, one of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to the output terminal of the second inverter,

wherein each of the first inverter and the second inverter includes;

a third transistor having a gate, a source, and a drain,

a fourth transistor having a gate, a source, and a drain,

a first terminal electrically connected to the gate of the fourth transistor;

a second terminal electrically connected to a portion where the fourth transistor is connected to the third transistor,

wherein a high power supply voltage terminal is electrically connected to one of the source and the drain of the third transistor, and the gate of the third transistor is electrically connected to the other of the source and the drain of the third transistor;

wherein one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and a low power supply voltage terminal is electrically connected to the other of the source and the drain of the fourth transistor;

wherein each of the third transistor and the fourth transistor includes;

a gate electrode;

a gate insulating layer provided over the gate electrode;

an oxide semiconductor layer provided over the gate insulating layer; and

a source electrode and a drain electrode in contact with part of the oxide semiconductor layer,

wherein the fourth transistor includes a reduction prevention layer over the oxide semiconductor layer, the source electrode, and the drain electrode, and

wherein the third transistor does not include a reduction prevention layer over the oxide semiconductor layer, the source electrode, and the drain electrode.

17. The logic circuit according to claim 16, wherein the fourth transistor includes an oxygen vacancy control region between the source electrode and the drain electrode over a surface of the oxide semiconductor layer, which is opposite to a surface in contact with the gate insulating layer.

18. The logic circuit according to claim 16, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

19. The logic circuit according to claim 16, wherein the third transistor and the fourth transistor have the same conductivity type.

20. The logic circuit according to claim 16, wherein one of the source electrode and the drain electrode of the fourth transistor is in contact with the gate electrode of the third transistor through an opening portion provided in the gate insulating layer.