Scalable High Performance 3D Graphics

• US 20110221742A1
• Filed: 10/05/2010
• Published: 09/15/2011
• Est. Priority Date: 03/22/2002
• Status: Active Grant

• Current Assignee: Gamehancement LLC (Jeffrey M. Gross)
• Original Assignee: Michael F. Deering
• Inventors: Deering, Michael F., Lavelle, Michael G.
• Granted Patent: US 8,593,468 B2
• Time in Patent Office: Days
• US Class Current: 345/419
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 5/70 Denoising; Smoothing

Abstract

A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Claims

1. A method for accelerating 3D graphics using a plurality of nodes connected to a ring, the method comprising:

receiving packets from a neighboring node on the ring and transmitting packets to another neighboring node on the ring;

receiving graphics primitive loop packets, executing the graphics rendering specified in the graphics primitive loop packets including accessing via a memory port a texture store in a local memory sub-system as required by the graphics primitive loop packet, and generating corresponding draw pixel loop packets;

receiving draw pixel loop packets and, as specified by the draw pixel loop packets, performing via the memory port a conditional sample update function of samples and/or pixels in an interleave of a super-sampled frame buffer stored in the local memory sub-system; and

receiving video pixel loop packets via the loop interface and, as specified by the video pixel loop packets, retrieving via the memory port samples and/or pixels in the interleave stored in the local memory sub-system to modify the video pixel loop packets, and transmitting the modified video pixel loop packets via the loop interface.