METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE TO REDUCE FLOATING-GATE-TO-FLOATING-GATE COUPLING EFFECT

• US 20110222352A1
• Filed: 05/26/2011
• Published: 09/15/2011
• Est. Priority Date: 06/06/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Granted Patent: US 8,462,548 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data. One of the lower page or the upper page of the predetermined memory cells is reprogrammed with the first or second predetermined data, respectively.

Claims

1. A device comprising:

a plurality of memory cells, each cell adapted to store a lower page of data and an upper page of data; and

a controller circuit coupled to the plurality of memory cells, the controller circuit configured to program a memory cell of the plurality of memory cells such that first data is programmed in the lower page of the memory cell and second data is programmed in the upper page of the memory cell and the controller circuit is further configured to reprogram, with the second data, only the upper page of only a logical state having a widest threshold voltage distribution of the memory cell.

2. The device of claim 1 wherein the non-volatile memory device is a NAND flash memory device.

3. The device of claim 1 wherein the controller circuit is further adapted to read a state of a first programmed cell having a first verify voltage, generate a bit line voltage in response to the read state, bias the bit line coupled to the first programmed cell with the bit line voltage, and reprogram the upper page of the first programmed cell.

4. A system comprising:

a processor configured to generate memory signals; and

a memory device coupled to the processor and configured to operate in response to the memory signals, the device comprising;

a plurality of memory cells, each cell configured to store a lower page of data and an upper page of data; and

a controller circuit coupled to the memory array, the controller circuit configured to program a memory cell of the plurality of memory cells such that first data is programmed in the lower page of the memory cell and second data is programmed in the upper page of the memory cell and the controller circuit is further configured to reprogram, with the second data, only the upper page of only a logical state having a widest threshold voltage distribution of the memory cell.

5. The system of claim 4 wherein the memory signals comprise control signals, data signals, and address signals.

6. The system of claim 4 wherein the controller circuit is further configured to program the predetermined memory cells such that the lower pages of a pair of adjacent odd and even bit lines are programmed substantially simultaneously with a first data bit and the upper pages of the pair of adjacent odd and even bit lines are programmed substantially simultaneously with a second data bit.

7. A device comprising:

a plurality of memory cells; and

a controller circuit configured to;

program a memory cell of the plurality of memory cells such that first data is programmed in a lower page of the memory cell and second data is programmed in an upper page of the memory cell;

program a memory cell of the plurality of memory cells that is adjacent to the memory cell; and

reprogram one of the first data or the second data into the memory cell after the adjacent memory cell is programmed.

8. The device of claim 7, wherein the controller circuit being configured to reprogram one of the first data or the second data into the memory cell after the adjacent memory cell is programmed comprises the controller circuit being configured to reprogram the second data into the upper page of the memory cell.

9. The device of claim 8, wherein the controller circuit being configured to reprogram the second data into the upper page of the memory cell comprises the controller circuit being configured to reprogram only the upper page of the memory cell.

10. The device of claim 7, wherein the controller circuit being configured to reprogram one of the first data or the second data into the memory cell after the adjacent memory cell is programmed comprises the controller circuit being configured to:

read a state of the memory cell;

determine a bit line voltage in response to the read state; and

reprogram the second data into the upper page of the memory cell using the bit line voltage.

11. The device of claim 7, wherein the controller circuit being configured to reprogram one of the first data or the second data into the memory cell after the adjacent memory cell is programmed comprises the controller circuit being configured to reprogram the first data into the lower page of the memory cell.

12. The device of claim 11, wherein the controller circuit being configured to reprogram the first page into the upper page of the memory cell comprises the controller circuit being configured to reprogram only the lower page of the memory cell.

13. The device of claim 7, wherein the controller circuit is configured to program the first data in the lower page of the memory cell before programming a lower page of the adjacent memory cell, program the second data in the upper page of the memory cell before programming an upper page of the adjacent memory cell, and reprogram the second data into the memory cell after the lower and upper pages of the adjacent memory cell are programmed.

14. The device of claim 7, wherein the controller circuit is configured to program the first data in the lower page of the memory cell before programming the second data in the upper page of the memory cell, program a lower page of the adjacent memory cell before programming an upper page of the adjacent memory cell, and reprogram the second data into the memory cell after the lower and upper pages of the adjacent memory cell are programmed.

15. The device of claim 7, wherein the controller circuit comprises control circuitry of a memory device.

16. The device of claim 7, wherein the controller circuit being configured to reprogram one of the first data or the second data into the memory cell after the adjacent memory cell is programmed comprises the controller circuit being configured to reprogram second data into the upper page of the memory cell only if the second data being reprogrammed into the upper page of the memory cell corresponds to the logical state having the widest threshold voltage distribution.

17. The device of claim 7, wherein the controller circuit being configured to reprogram one of the first data or the second data into the memory cell after the adjacent memory cell is programmed comprises the controller circuit being configured to reprogram second data into the upper page of the memory cell only if the second data being reprogrammed into the upper page of the memory cell corresponds to one of the logical states having the two widest threshold voltage distributions.