High-Speed Communication Channel Techniques with Improved Robustness to Timing Uncertainty

• US 20110222635A1
• Filed: 03/29/2011
• Published: 09/15/2011
• Est. Priority Date: 11/12/2002
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Quellan, Inc. (Renesas Electronics Corporation)
• Inventors: Kim, Andrew Joo, Bajekal, Sanjay, Ralph, Stephen E.
• Granted Patent: US 8,219,893 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H03M 1/0675 using redundancy
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection

Abstract

A method and system using the principle of generalized maximum likelihood estimation to resolve sample timing uncertainties that are associated with the decoding of communication signals. By using generalized maximum likelihood estimation, sample timing uncertainty can be resolved by taking multiple samples of the received signal within a symbol period and determining which sample best corresponds to the optimal sample timing. The sample which best corresponds to the optimal sample timing can be determined from a timing index which can be calculated from ambiguity indicators that are based on the samples of the received signal.

Claims

1-20. -20. (canceled)

21. A communication system, comprising:

a receiver comprising an input configured to receive a signal; and

a plurality of soft-decoders, each soft-decoder operable to sample the received signal at a different time within a symbol period and to output two values for each sample, the first value comprising a preliminary decoded value and the second value comprising an ambiguity indicator; and

a logic device coupled to the each of the soft-decoders, operable to determine a decoded value for each symbol based on one or more preliminary decoded values and ambiguity indicators.

22. The communication system of claim 21, wherein the soft-decoders are substantially identical to one another.

23. The communication system of claim 21, wherein each soft-decoder comprises:

a first comparator with inputs comprising the received signal and a first reference voltage;

a second comparator with inputs comprising the received signal and a second reference voltage; and

a third comparator with inputs comprising the received signal and a third reference voltage.

24. The communication system of claim 21, wherein each soft-decoder comprises a plurality of comparators and one or more logical AND gates.

25. The communication system of claim 21, further comprising a plurality of delay elements coupled to the soft-decoders.

26. The communication system of claim 21, further comprising a plurality of delay elements coupled to the soft-decoders, each delay element delaying the received signal by a different amount.

27. The communication system of claim 21, further comprising a plurality of delay elements coupled to the soft-decoders, each delay element delaying a clock signal by a different amount.

28. The communication system of claim 21, wherein the logic device determines the decoded value for each symbol using generalized maximum likelihood estimation with the one or more preliminary decoded values and ambiguity indicators.

29. The communication system of claim 21, wherein the received signal comprises a multi-level signal.

30. A communication system, comprising:

a transmitter that is operable to transmit a multi-level signal;

a receiver for receiving the multi-level signal over a communication path extending between the receiver and the transmitter, the receiver comprising;

an asynchronous soft-decoder that is operable to continuously sample the multi-level signal and produce a decoded output signal and an ambiguous indicator signal;

a plurality of first delay elements coupled to a first soft-decoder, each first delay element operable to generate a different delay relative to another first delay element and to produce an ambiguity indicator from the ambiguous indicator signal;

a plurality of second delay elements coupled to a second soft-decoder output, each second delay element operable to generate a different delay relative to another second delay element and to produce a preliminary decoded output from the decoded output signal; and

a logic device coupled to the each of the first and second delay elements, for determining a decoded value based on one or more of the preliminary decoded outputs and ambiguity indicators.

31. The communication system of claim 30, wherein the soft-decoder comprises:

a first comparator with inputs comprising the multi-level signal and a first reference voltage;

a second comparator with inputs comprising the multi-level signal and a second reference voltage; and

a third comparator with inputs comprising the multi-level signal and a third reference voltage.

32. The communication system of claim 30, wherein the soft-decoder comprises a plurality of comparators and one or more logical AND gates.

33. The communication system of claim 30, wherein the logic device determines the decoded value for each symbol using generalized maximum likelihood estimation with the one or more preliminary decoded values and ambiguity indicators.

34. A signal receiver, comprising:

an input for receiving a signal;

an analog-to-digital converter for sampling the received signal faster than once every symbol period of the received signal and outputting for each sample a first value comprising a preliminary decoded value and a second value comprising an ambiguity indicator;

a processor coupled to the converter and operable to;

group a subset of sampled first and second values derived from the single symbol period;

examine the subset of sampled first and second values; and

determine a first value closest to an optimum sampling time based on a principle of generalized maximum likelihood, for decoding the first value closest to the optimum sampling time and outputting that decoded first value as the decoded symbol.

35. The signal receiver of claim 34, further comprising a clock recovery unit coupled to the converter for providing a clock signal.

36. The signal receiver of claim 34, wherein the processor calculates the first value closest to the optimum sampling time by:

computing an absolute difference between each first value and a nearest level corresponding to a decoded symbol;

finding a first value which has a smallest absolute difference from the subset of first values; and

taking the first value with the smallest absolute difference as the first value closest to the optimum sampling time.

37. A communication system, comprising:

a receiver comprising an input for receiving a signal; and

a decoding unit that estimates a timing offset for the received signal on a symbol-by-symbol basis and decodes the received signal using generalized maximum likelihood estimation with the estimated timing offset, the decoding unit comprising;

a signal splitting element that divides the received signal into a plurality of received signals; and

a plurality of delay elements that each delay one of the plurality of received signals, wherein each delay element applies a different time delay than each other delay element.

38. The communication system of claim 37, wherein the decoding unit decodes the received signal using generalized maximum likelihood estimation by identifying a symbol that corresponds to a selected timing index.

39. The communication system of claim 37, wherein the received signal comprises a multi-level signal.

40. The communication system of claim 37, wherein the decoding unit further comprises a plurality of soft-decoders, each soft-decoder coupled to a respective delay element, and wherein each soft decoder samples the received signal at a different time within a symbol period and outputs two values for each sample, the first value comprising a preliminary decoded value and the second value comprising an ambiguity indicator.

41. The communication system of claim 40, wherein the soft-decoders are substantially identical to one another.

42. The communication system of claim 40, wherein each soft-decoder comprises:

a first comparator with inputs comprising the received signal and a first reference voltage;

a second comparator with inputs comprising the received signal and a second reference voltage; and

a third comparator with inputs comprising the received signal and a third reference voltage.

43. The communication system of claim 40, wherein each soft-decoder comprises a plurality of comparators and one or more logical AND gates.