Continuous Power Transfer Scheme for Two-Wire Serial Link

• US 20110222682A1
• Filed: 04/28/2011
• Published: 09/15/2011
• Est. Priority Date: 06/23/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Yoder, James D., Bark, Boris A., Kiss, Peter, Ransijn, Johannes G.
• Granted Patent: US 8,442,212 B2
• Time in Patent Office: Days
• US Class Current: 379/390.01
• CPC Class Codes: H04M 19/001 Current supply source at the exchanger providing current to substations
• CPC Class Codes: H04M 3/005 Interface circuits for subscriber lines current supply H04M19/00 and subgroups; supervisory, monitoring or testing arrangements H04M3/22 and subgroups; in key telephone systems H04M9/006

Abstract

The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.

Claims

1. A method for low-ripple transfer of power from a system-side circuit to a line-side circuit connected via a two-wire interface, comprising the steps of:

transmitting a forward pulse stream from the system-side circuit to the line-side circuit during a first time period;

rectifying the forward pulse stream in the line-side circuit to produce a first rectified voltage during the first time period;

transmitting a reverse pulse stream from the line-side circuit to the system-side circuit during a second time period;

providing a supplemental pulse stream during the second time period; and

rectifying the supplemental pulse stream in the line-side circuit to produce a second rectified voltage during the second time period;

wherein a rectified voltage is produced during both the first and second time periods.

2. The method of claim 1, wherein the step of providing a supplemental pulse stream comprises the steps of:

receiving, at the system-side circuit, the reverse pulse stream from the line-side circuit;

reinforcing, at the system-side circuit, the reverse pulse stream to produce the supplemental pulse stream; and

transferring the supplemental pulse stream from the system-side circuit to the line-side circuit.

3. The method of claim 1, further comprising the steps of latching to each pulse in the reverse pulse stream.

4. An apparatus for low-ripple transfer of power from a system-side circuit to a line-side circuit connected via a two-wire interface, comprising:

a means for transmitting a forward pulse stream from the system-side circuit to the line-side circuit during a first time period;

a means for rectifying the forward pulse stream in the line-side circuit to produce a first rectified voltage during the first time period;

a means for transmitting a reverse pulse stream from the line-side circuit to the system-side circuit during a second time period;

a means for providing a supplemental pulse stream during the second time period; and

a means for rectifying the supplemental pulse stream in the line-side circuit to produce a second rectified voltage during the second time period;

wherein a rectified voltage is produced during both the first and second time periods.

5. The apparatus of claim 4, wherein the means for providing a supplemental pulse stream comprises:

a means for receiving, at the system-side circuit, the reverse pulse stream from the line-side circuit;

a means for reinforcing, at the system-side circuit, the reverse pulse stream to produce the supplemental pulse stream; and

a means for transferring the supplemental pulse stream from the system-side circuit to the line-side circuit.

6. The apparatus of claim 4, further comprising a means for latching to each pulse in the reverse pulse stream.

7. A method of interfacing a first circuit with a second circuit having a tri-state buffer connected between a storage device and ground, the tri-state buffer including an input terminal, an enable terminal, and an output terminal, comprising the steps of:

receiving a first signal having an AC-frequency component at the output terminal of the tri-state buffer, and

switching the tri-state buffer, such that (i) during a first time period, the first signal is electrically connected to the storage capacitor, and (ii) during a second time period, the first signal is electrically connected to ground.

8. The method of claim 7, wherein:

during the first time period the voltage of the first signal is above a first predetermined level; and

during the second time period the voltage of the first signal is below a second predetermined level.

9. The method of claim 8, wherein:

the first predetermined level is approximately the voltage at the storage device, and the second predetermined level is approximately the voltage at ground.

10. The method of claim 7, wherein the tri-state buffer is switched in substantial synchronism with the first signal.

11. The method of claim 10, wherein the step of switching comprises inputting at least a portion of the first signal to the input terminal of the tri-state buffer.

12. The method of claim 11, wherein the steps of receiving, switching, and inputting are performed during a first portion of a frame including the first and second time periods.

13. The method of claim 12, further comprising inputting, during a second portion of the frame, a second signal to the input terminal of the tri-state buffer, such that the second signal is passed to the output terminal of the tri-state buffer during the second portion of the frame.

14. The method of claim 13, wherein the steps of inputting the first signal and inputting the second signal to the input terminal of the tri-state buffer comprise the steps of:

inputting the first signal and the second signal to a mode selection switch;

providing a mode selection signal to the mode selection switch that causes the mode selection switch to select and output either the first signal or the second signal to the input terminal of the tri-state buffer.

15. An apparatus for interfacing a first circuit with a second circuit having a tri-state buffer connected between a storage device and ground, the tri-state buffer including an input terminal, an enable terminal, and an output terminal, the apparatus comprising:

a means for receiving a first signal having an AC-frequency component at the output terminal of the tri-state buffer, and a means for switching the tri-state buffer, such that (i) during a first time period, the first signal is electrically connected to the storage capacitor, and (ii) during a second time period, the first signal is electrically connected to ground.