METHODS OF FORMING AN ARRAY OF MEMORY CELLS, METHODS OF FORMING A PLURALITY OF FIELD EFFECT TRANSISTORS, METHODS OF FORMING SOURCE/DRAIN REGIONS AND ISOLATION TRENCHES, AND METHODS OF FORMING A SERIES OF SPACED TRENCHES INTO A SUBSTRATE

• US 20110223734A1
• Filed: 03/09/2010
• Published: 09/15/2011
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Housley, Richard, Davis, Neal L., Khurana, Ranjan
• Granted Patent: US 8,039,340 B2
• Time in Patent Office: Days
• US Class Current: 438/296
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Claims

1-11. -11. (canceled)

12. A method of forming a plurality of field effect transistors, comprising:

forming a plurality of spaced lines over semiconductive material of a semiconductor substrate;

forming pairs of first and second anisotropically etched sidewall spacers on opposing sides of the spaced lines, individual of the lines having greater maximum width than minimum width of space between immediately adjacent of the first and second spacers between immediately adjacent of the lines;

removing the spaced lines from between the first and second spacers to form a mask comprising alternating first and second mask openings, the first mask openings being located where the spaced lines were located and being wider than the second mask openings, the respective first openings having laterally innermost edges defined by laterally innermost edges of the first and second spacers, the respective second openings having laterally innermost edges defined by laterally outermost edges of the first and second spacers;

using the mask, etching both inter-transistor trenches and intra-transistor trenches simultaneously into the semiconductive material, the inter-transistor trenches being formed through the first mask openings, the intra-transistor trenches being formed through the second mask openings, the inter-transistor trenches being etched wider and deeper within the semiconductive material than are the intra-transistor trenches;

providing a pair of source/drain regions within the semiconductive material on opposing sides of individual of the intra-transistor trenches between immediately adjacent of the inter-transistor trenches;

providing a channel region within the semiconductive material elevationally inward of the pair of source/drain regions between immediately adjacent of the inter-transistor trenches; and

providing a gate operably proximate the channel region.

13. The method of claim 12 comprising filling the inter-transistor trenches with dielectric material.

14. The method of claim 12 comprising filling the intra-transistor trenches with dielectric material.

15. The method of claim 12 comprising filling both the inter-transistor trenches and the intra-transistor trenches with dielectric material.

16. The method of claim 15 wherein the filling comprises depositing the same dielectric material at the same time to within both the inter-transistor trenches and the intra-transistor trenches.

17. The method of claim 16 comprising continuing the depositing until both the inter-transistor trenches and the intra-transistor trenches have been overfilled with said same dielectric material.

21. The method of claim 12 comprising forming the gate to comprise a portion of one of a plurality of gate lines, and forming the plurality of gate lines to extend orthogonally relative to the inter-transistor trenches.

22. The method of claim 21 comprising forming the gate to comprise portions of two of the plurality of gate lines.

24. The method of claim 12 wherein forming the spaced lines comprises:

forming precursor lines individually having width greater than said maximum width; and

laterally trimming the width of the precursor lines.

18-20. -20. (canceled)

23. (canceled)

25-32. -32. (canceled)