Mapping between registers used by multiple instruction sets

• US 20110225397A1
• Filed: 02/22/2011
• Published: 09/15/2011
• Est. Priority Date: 03/15/2010
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Seal, David James, Grisenthwaite, Richard Roy
• Granted Patent: US 9,092,215 B2
• Time in Patent Office: Days
• US Class Current: 712/208
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.

Claims

1. Apparatus for processing data comprising:

a plurality of registers configured to store data values to be processed;

processing circuitry coupled to said plurality of registers and configured to perform data processing operations upon data values stored in said plurality of registers;

an instruction decoder coupled to said processing circuitry and responsive to a stream of program instructions to control said processing circuitry to perform said data processing operations;

wherein

said instruction decoder is responsive to program instructions of a first instruction set to control said processing circuitry to perform said data processing operations using N-bit architectural registers provided by said plurality of registers, where N is a positive integer value;

said instruction decoder is responsive to program instructions of a second instruction set to control said processing circuitry to perform said data processing operations using M-bit architectural registers provided by said plurality of registers, where M is a positive integer value and at least some of said plurality of registers are shared by program instructions of said first instruction set and program instructions of said second instruction set;

said instruction decoder is configured to decode a register specifying field within a program instruction of said first instruction set when determining which of said plurality of registers to access as part of a first set of N-bit architectural registers presented for use by program instructions of said first instruction set;

said instruction decoder is configured to decode a register specifying field within a program instruction of said second instruction set when determining which of said plurality of registers to access as part of a second set of M-bit architectural registers presented for use by program instructions of said second instruction set; and

said instruction decoder is configured to provide a first mapping between values of said register specifying field within program instructions of said first instruction set and said plurality of registers and a second mapping between values of said register specifying field within program instructions of said second instruction set and said plurality of registers, said first mapping being different to said second mapping and said first mapping and said second mapping being such that each register of said first set has a predetermined one-to-one mapping to a register of said second set, shares with said register of said second set a shared part of a common register within said plurality of registers, an unshared part of said common register being unaccessible using instructions of said first instruction set, and stores a value that is accessible using a register of said second set.

2. Apparatus as claimed in claim 1, wherein M=2N.

3. Apparatus as claimed in claim 1, wherein said first set and said second set include a common number of registers.

4. Apparatus as claimed in claim 1, wherein said plurality of registers comprises a plurality of M-bit registers and program instructions of said first instruction set access a least significant N-bits of said M-bit registers.

5. Apparatus as claimed in claim 1, wherein N=32.

6. Apparatus as claimed in claim 1, wherein said apparatus when executing program instructions of said first instruction set is configured to operate in a plurality of exception states and said instruction decoder is configured to decode said register specifying field within a program instruction of said first instruction set together with a current exception state of said plurality of exception states when determining which of said plurality of registers to access and a group of registers within said first set corresponding to a common value of said register specifying field within said program instruction of said first instruction set and different exception states are a banked group of registers.

7. Apparatus as claimed in claim 6, wherein within said banked group of registers a value of a least significant bit of said register specifying field within said program instruction of said first instruction set is common with a value of a least significant bit of said register specifying field within said program instruction of said second instruction set.

8. Apparatus as claimed in claim 7, wherein said instruction decoder is configured to provide said mapping such that for a portion of said registers of said second set corresponding to a sequence of incrementing values of said register specifying field within said program instruction of said second instruction set, corresponding values of said register specifying field within said program instruction of said first instruction set alternate between two values.

9. Apparatus as claimed in claim 1, wherein said plurality of registers include a null value register storing a predetermined null value when accessed with a program instruction of said second instruction set.

10. Apparatus as claimed in claim 9, wherein said first set of registers has no architectural register mapped to said null value register.

11. Apparatus as claimed in claim 1, wherein, when executing program instructions of said first instruction set, a program counter register stores a value indicative of a memory address of a program instruction being executed and said program counter register is outside said first set that are mapped to registers of said second set.

12. Apparatus as claimed in claim 1, wherein when said common register is accessed by a program instruction of said first instruction set, said unshared part is one of zeroed, unaltered and set to an undefined value.

26. A virtual machine provided by a computer program executing upon a data processing apparatus, said virtual machine providing an instruction execution environment corresponding to the apparatus of claim 1.

13. Apparatus for processing data comprising:

a plurality of register means for storing data values to be processed;

processing means for performing data processing operations upon data values stored in said plurality of register means;

instruction decoding means for controlling said processing circuitry to perform said data processing operations in response to a stream of program instructions;

wherein

said instruction decoding means is responsive to program instructions of a first instruction set to control said processing means to perform said data processing operations using N-bit architectural register means provided by said plurality of register means, where N is a positive integer value;

said instruction decoding means is responsive to program instructions of a second instruction set to control said processing means to perform said data processing operations using M-bit architectural register means provided by said plurality of register means, where M is a positive integer value and at least some of said plurality of register means are shared by program instructions of said first instruction set and program instructions of said second instruction set;

said instruction decoding means is configured to decode a register specifying field within a program instruction of said first instruction set when determining which of said plurality of register means to access as part of a first set of N-bit architectural register means presented for use by program instructions of said first instruction set;

said instruction decoding means is configured to decode a register specifying field within a program instruction of said second instruction set when determining which of said plurality of register means to access as part of a second set of M-bit architectural register means presented for use by program instructions of said second instruction set; and

said instruction decoding means is configured to provide a first mapping between values of said register specifying field within program instructions of said first instruction set and said plurality of register means and a second mapping between values of said register specifying field within program instructions of said second instruction set and said plurality of register means, said first mapping being different to said second mapping and said first mapping and said second mapping being such that each register means of said first set has a predetermined one-to-one mapping to a register means of said second set, shares with said register means of said second set a shared part of a common register means within said plurality of register means, an unshared part of said common register means being unaccessible using instructions of said first instruction set, and stores a value that is accessible using a register means of said second set.

14. A method of processing data comprising the steps of:

storing data values to be processed in a plurality of registers;

performing data processing operations upon data values stored in said plurality of registers;

decoding a stream of program instructions to control said performing of said data processing operations;

wherein

said decoding is responsive to program instructions of a first instruction set to control said performing of said data processing operations using N-bit architectural registers provided by said plurality of registers, where N is a positive integer value;

said decoding is responsive to program instructions of a second instruction set to control said performing of said data processing operations using M-bit architectural registers provided by said plurality of registers, where M is a positive integer value and at least some of said plurality of registers are shared by program instructions of said first instruction set and program instructions of said second instruction set;

said decoding decodes a register specifying field within a program instruction of said first instruction set when determining which of said plurality of registers to access as part of a first set of N-bit architectural registers presented for use by program instructions of said first instruction set;

said decoding decodes a register specifying field within a program instruction of said second instruction set when determining which of said plurality of registers to access as part of a second set of M-bit architectural registers presented for use by program instructions of said second instruction set; and

said decoding provides a first mapping between values of said register specifying field within program instructions of said first instruction set and said plurality of registers and a second mapping between values of said register specifying field within program instructions of said second instruction set and said plurality of registers, said first mapping being different to said second mapping and said first mapping and said second mapping being such that each register of said first set has a predetermined one-to-one mapping to a register of said second set, shares with said register of said second set a shared part of a common register within said plurality of registers, an unshared part of said common register being unaccessible using instructions of said first instruction set, and stores a value that is accessible using a register of said second set.

15. A method as claimed in claim 14, wherein M=2N.

16. A method as claimed in claim 14, wherein said first set and said second set include a common number of registers.

17. A method as claimed in claim 14, wherein said plurality of registers comprises a plurality of M-bit registers and program instructions of said first instruction set access a least significant N-bits of said M-bit registers.

18. A method as claimed in claim 14, wherein N=32.

19. A method as claimed in claim 14, wherein when executing program instructions of said first instruction set, operating in one of a plurality of exception states and said decoding decodes said register specifying field within a program instruction of said first instruction set together with a current exception state of said plurality of exception states when determining which of said plurality of registers to access, and a group of registers within said first set corresponding to a common value of said register specifying field within said program instruction of said first instruction set and different exception states being a banked group of registers.

20. A method as claimed in claim 19, wherein within said banked group of registers a value of a least significant bit of said register specifying field within said program instruction of said first instruction set is common with a value of a least significant bit of said register specifying field within said program instruction of said second instruction set.

21. A method as claimed in claim 20, wherein said decoding provides said mapping such that for a portion of said registers of said second set corresponding to a sequence of incrementing values of said register specifying field within said program instruction of said second instruction set, corresponding values of said register specifying field within said program instruction of said first instruction set alternate between two values.

22. A method as claimed in claim 14, wherein said plurality of registers include a null value register storing a predetermined null value when accessed with a program instruction of said second instruction set.

23. A method as claimed in claim 22, wherein said first set of registers has no architectural register mapped to said null value register.

24. A method as claimed in claim 14, wherein, when executing program instructions of said first instruction set, a program counter register stores a value indicative of a memory address of a program instruction being executed and said program counter register is outside said first set of registers that are mapped to registers of said second set.

25. A method as claimed in claim 14 wherein when said common register is accessed by a program instruction of said first instruction set, said unshared part is one of zeroed, unaltered and set to an undefined value.

27. Apparatus for processing data comprising:

a plurality of registers configured to store data values to be processed;

processing circuitry coupled to said plurality of registers and configured to perform data processing operations upon data values stored in said plurality of registers;

an instruction decoder coupled to said processing circuitry and responsive to a stream of program instructions to control said processing circuitry to perform said data processing operations;

wherein

said instruction decoder is responsive to program instructions of a first instruction set to control said processing circuitry to perform said data processing operations using a first set of architectural registers provided by said plurality of registers;

said apparatus when executing program instructions of said first instruction set is configured to operate in a plurality of exception states and said instruction decoder is configured to decode said register specifying field within a program instruction of said first instruction set together with a current exception state of said plurality of exception states when determining which architectural register to use;

said instruction decoder is responsive to program instructions of a second instruction set to control said processing circuitry to perform said data processing operations using a second set of architectural registers provided by said plurality of registers and shared with program instructions of said first instruction set; and

said instruction decoder is configured to decode a register specifying field within a program instruction of said second instruction set without a dependence upon exception state when determining which architectural register to use.

28. Apparatus as claimed in claim 27, wherein said first set and said second set include a common number of registers.

29. Apparatus as claimed in claim 27, wherein said plurality of registers comprises a plurality of 2N-bit registers and program instructions of said first instruction set access a least significant N-bits of said 2N-bit registers.

30. Apparatus as claimed in claim 29, wherein N=32.

31. Apparatus as claimed in claim 27, wherein a group of registers within said first set corresponding to a common value of said register specifying field within said program instruction of said first instruction set and different exception states are a banked group of registers.

32. Apparatus as claimed in claim 31, wherein within said banked group of registers a value of a least significant bit of said register specifying field within said program instruction of said first instruction set is common with a value of a least significant bit of said register specifying field within said program instruction of said second instruction set.

33. Apparatus as claimed in claim 32, wherein said instruction decoder is configured such that for a portion of said registers of said second set corresponding to a sequence of incrementing values of said register specifying field within said program instruction of said second instruction set, corresponding values of said register specifying field within said program instruction of said first instruction set alternate between two values.

34. Apparatus as claimed in claim 27, wherein said plurality of registers include a null value register storing a predetermined null value when accessed with a program instruction of said second instruction set, said first set having no register corresponding to said null value register.

35. Apparatus as claimed in claim 34, wherein said first set has no architectural register corresponding to said null value register.

36. Apparatus as claimed in claim 27, wherein, when executing program instructions of said first instruction set, a program counter register stores a value indicative of a memory address of a program instruction being executed and said program counter register is outside said first set that correspond to registers of said second set.

48. A virtual machine provided by a computer program executing upon a data processing apparatus, said virtual machine providing an instruction execution environment corresponding to the apparatus of claims 27.

37. Apparatus for processing data comprising:

a plurality of register means for storing data values to be processed;

processing means for performing data processing operations upon data values stored in said plurality of register means;

instruction decoding means for controlling said processing circuitry to perform said data processing operations in response to a stream of program instructions;

wherein

said instruction decoder means is responsive to program instructions of a first instruction set to control said processing means to perform said data processing operations using a first set of architectural registers provided by said plurality of register means;

said apparatus when executing program instructions of said first instruction set is configured to operate in a plurality of exception states and said instruction decoder means is configured to decode said register specifying field within a program instruction of said first instruction set together with a current exception state of said plurality of exception states when determining which architectural register to use;

said instruction decoder means is responsive to program instructions of a second instruction set to control said processing means to perform said data processing operations using a second set of architectural registers provided by said plurality of register means and shared with program instructions of said first instruction set; and

said instruction decoder means is configured to decode a register specifying field within a program instruction of said second instruction set without a dependence upon exception state when determining which of architectural register to use.

38. A method of processing data comprising the steps of:

storing data values to be processed in a plurality of registers;

performing data processing operations upon data values stored in said plurality of registers;

decoding a stream of program instructions to control said performing of said data processing operations;

wherein

said decoding is responsive to program instructions of a first instruction set to control said performing of said data processing operations using a first set of architectural registers provided by said plurality of registers;

when executing program instructions of said first instruction set, operating in one of a plurality of exception states and decoding a register specifying field within a program instruction of said first instruction set together with a current exception state of said plurality of exception states to determine which architectural register to use;

said decoding is responsive to program instructions of a second instruction set to control said performing of said data processing operations using a second set of architectural registers provided by said plurality of registers and shared with program instructions of said first instruction set; and

said decoding decodes a register specifying field within a program instruction of said second instruction set without a dependence upon exception state when determining which architectural register to use.

39. A method as claimed in claim 38, wherein said first set and said second set include a common number of registers.

40. A method as claimed in claim 38, wherein said plurality of registers comprises a plurality of 2N-bit registers and program instructions of said first instruction set access a least significant N-bits of said 2N-bit registers.

41. A method as claimed in claim 40, wherein N=32.

42. A method as claimed in claim 38, wherein a group of registers within said first set corresponding to a common value of said register specifying field within said program instruction of said first instruction set and different exception states are a banked group of registers.

43. A method as claimed in claim 42, wherein within said banked group of registers a value of a least significant bit of said register specifying field within said program instruction of said first instruction set is common with a value of a least significant bit of said register specifying field within said program instruction of said second instruction set.

44. A method as claimed in claim 43, wherein said decoding is such that for a portion of said registers of said second set corresponding to a sequence of incrementing values of said register specifying field within said program instruction of said second instruction set, corresponding values of said register specifying field within said program instruction of said first instruction set alternate between two values.

45. A method as claimed in claim 38, wherein said plurality of registers include a null value register storing a predetermined null value when accessed with a program instruction of said second instruction set, said first set having no register corresponding to said null value register.

46. A method as claimed in claim 45, wherein said first set has no architectural register corresponding to said null value register.

47. A method as claimed in claim 38, wherein, when executing program instructions of said first instruction set, a program counter register stores a value indicative of a memory address of a program instruction being executed and said program counter register is outside said first set that correspond to registers of said second set.