BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS

• US 20110227028A1
• Filed: 03/14/2011
• Published: 09/22/2011
• Est. Priority Date: 03/16/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Kreupl, Franz, Makala, Raghuveer S., Sekar, Deepak Chandra
• Granted Patent: US 8,354,660 B2
• Time in Patent Office: Days
• US Class Current: 257/4
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

In a first aspect, an MIM stack is provided that includes (1) a first conductive layer comprising a first metal-silicide layer and a second metal-silicide layer; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.

Claims

1. A metal-insulator-metal (MIM) stack comprising:

a first conductive layer comprising a first metal-silicide layer and a second metal-silicide layer;

a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and

a second conductive layer formed above the resistivity-switching layer.

2. The MIM stack of claim 1 wherein the first metal-silicide layer comprises one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide and the second metal-silicide layer comprises a different one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide.

3. The MIM stack of claim 1 wherein the first metal-silicide layer comprises nickel silicide and the second metal-silicide layer comprises titanium silicide.

4. The MIM stack of claim 1 wherein the first metal-silicide layer comprises cobalt silicide and the second metal-silicide layer comprises titanium silicide.

5. The MIM stack of claim 1 wherein the first metal-silicide layer comprises titanium silicide and the second metal-silicide layer comprises tungsten silicide.

6. The MIM stack of claim 1 wherein the first conductive layer has a thickness of about 2-100 nanometers.

7. The MIM stack of claim 1 wherein the metal oxide layer comprises one or more of HfO_x, ZrO_x, NiO_x, TiO_x, TaO_x, NbO_x or Al_xO_y.

8. The MIM stack of claim 1 wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.

9. The MIM stack of claim 1 wherein the first conductive layer further comprises a metal or metal nitride having a Gibbs free energy of formation per O between about −

3 and −

6 eV.

10. The MIM stack of claim 9 wherein the first conductive layer comprises at least one of aluminum, aluminum nitride, lanthanum, lanthanum nitride, molybdenum, molybdenum nitride, tantalum, tantalum nitride, chromium, chromium nitride, hafnium, hafnium nitride, niobium, niobium nitride, vanadium, vanadium nitride, zirconium or zirconium nitride.

11. A memory cell comprising:

the MIM stack of claim 1; and

a steering element coupled to the MIM stack.

12. The memory cell of claim 11 wherein the steering element comprises a vertical polysilicon diode.

13. A method of forming a metal-insulator-metal (MIM) stack comprising:

forming a first conductive layer comprising a first metal-silicide layer and a second metal-silicide layer;

forming a resistivity-switching layer comprising a metal oxide layer above the first conductive layer; and

forming a second conductive layer above the resistivity-switching layer.

14. The method of claim 13 wherein the first metal-silicide layer comprises one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide and the second metal-silicide layer comprises a different one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide.

15. The method of claim 13 wherein the first metal-silicide layer comprises nickel silicide and the second metal-silicide layer comprises titanium silicide.

16. The method of claim 13 wherein the first metal-silicide layer comprises cobalt silicide and the second metal-silicide layer comprises titanium silicide.

17. The method of claim 13 wherein the first metal-silicide layer comprises titanium silicide and the second metal-silicide layer comprises tungsten silicide.

18. The method of claim 13 wherein the first conductive layer has a thickness of about 2-100 nanometers.

19. The method of claim 13 wherein the metal oxide layer comprises one or more of HfO_x, ZrO_x, NiO_x, TiO_x, TaO_x, NbO_x or Al_xO_y.

20. The method of claim 13 wherein forming the first conductive layer further comprises forming a metal or metal nitride having a Gibbs free energy of formation per O between about −

3 and −

6 eV.

21. A memory cell formed using the method of claim 13.

22. A metal-insulator-metal (MIM) stack comprising:

a first metal-silicide layer formed at a first temperature;

a second metal-silicide layer formed above the first metal-silicide layer and at a second temperature that is greater than the first temperature;

an n+ silicon or SiGe layer formed above the second metal-silicide layer;

a resistivity-switching layer comprising a metal oxide layer formed above the n+ silicon or SiGe layer; and

a second conductive layer formed above the resistivity-switching layer.

23. The MIM stack of claim 22 wherein the first metal-silicide layer comprises nickel silicide and the second metal-silicide layer comprises titanium silicide.

24. The MIM stack of claim 22 wherein the first metal-silicide layer comprises cobalt silicide and the second metal-silicide layer comprises titanium silicide.

25. The MIM stack of claim 22 wherein the first metal-silicide layer comprises titanium silicide and the second metal-silicide layer comprises tungsten silicide.

26. The MIM stack of claim 22 wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.

27. The MIM stack of claim 22 wherein the metal oxide layer comprises one or more of HfO_x, ZrO_x, NiO_x, TiO_x, TaO_x, NbO_x or Al_xO_y.

28. A memory cell comprising:

the MIM stack of claim 22; and

a steering element coupled to the MIM stack.

29. The memory cell of claim 28 wherein the steering element comprises a vertical polysilicon diode.

30. A method of forming a metal-insulator-metal (MIM) stack comprising:

forming a first metal-silicide layer at a first temperature;

forming a second metal-silicide layer above the first metal-silicide layer at a second temperature that is greater than the first temperature;

forming an n+ silicon or SiGe layer above the second metal-silicide layer;

forming a resistivity-switching layer comprising a metal oxide layer above the n+ silicon or SiGe layer; and

forming a second conductive layer above the resistivity-switching layer.

31. The method of claim 30 wherein the first metal-silicide layer comprises nickel silicide and the second metal-silicide layer comprises titanium silicide.

32. The method of claim 30 wherein the first metal-silicide layer comprises cobalt silicide and the second metal-silicide layer comprises titanium silicide.

33. The method of claim 30 wherein the first metal-silicide layer comprises titanium silicide and the second metal-silicide layer comprises tungsten silicide.

34. The method of claim 30 wherein the metal oxide layer comprises one or more of HfO_x, ZrO_x, NiO_x, TiO_x, TaO_x, NbO_x or Al_xO_y.

35. A memory cell formed by the method of claim 30.