SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110227060A1
• Filed: 09/22/2010
• Published: 09/22/2011
• Est. Priority Date: 09/24/2009
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro, Yamazaki, Shunpei, Sakakura, Masayuki, Miyanaga, Akiharu
• Application Number:
  US12/887,674
• Publication Number:
  US 20110227060A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

It is an object to provide a thin film transistor having favorable electric characteristics and high reliability and a semiconductor device which includes the thin film transistor as a switching element. An In—Ga—Zn—O-based film having an incubation state that shows an electron diffraction pattern, which is different from a conventionally known amorphous state where a halo shape pattern appears and from a conventionally known crystal state where a spot appears clearly, is formed. The In—Ga—Zn—O-based film having an incubation state is used for a channel formation region of a channel etched thin film transistor.

Claims

1. A semiconductor device comprising:

a thin film transistor, the thin film transistor comprising;

a channel formation region

wherein the channel formation region comprises an In—

Ga—

Zn—

O-based semiconductor,

wherein the In—

Ga—

Zn—

O-based semiconductor has an incubation state, wherein the incubation state of the In—

Ga—

Zn—

O-based semiconductor is neither a crystal state nor an amorphous state.

2. The semiconductor device according to claim 1, wherein the incubation state, the crystal state, or the amorphous state is analyzed by an electron diffraction pattern.

3. The semiconductor device according to claim 1,

wherein the incubation state is a state in which a spot thereof does not appear clearly but periodically in analysis of an electron diffraction pattern,

wherein the crystal state is a state in which a spot appears clearly in analysis of the electron diffraction pattern, and

wherein the amorphous state is a state in which a halo shape pattern appears in analysis of the electron diffraction pattern.

4. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a first insulating layer over the gate electrode layer;

an oxide semiconductor layer including indium, gallium, and zinc over the first insulating layer; and

a source electrode layer or a drain electrode layer over the oxide semiconductor layer;

wherein at least a region of the oxide semiconductor layer, with which the source electrode layer and the drain electrode layer do not overlap, has an incubation state, wherein the incubation state is neither a crystal state nor an amorphous state.

5. The semiconductor device according to claim 4, wherein the incubation state, the crystal state, or the amorphous state is analyzed by an electron diffraction pattern.

6. The semiconductor device according to claim 4 further comprising:

a second insulating layer which covers the source electrode layer or the drain electrode layer,

wherein the second insulating layer is in contact with the region of the oxide semiconductor layer, with which the source electrode layer and the drain electrode layer do not overlap.

7. The semiconductor device according to claim 4,

wherein the incubation state is a state in which a spot thereof does not appear clearly but periodically in analysis of an electron diffraction pattern,

wherein the crystal state is a state in which a spot appears clearly in analysis of the electron diffraction pattern, and

wherein the amorphous state is a state in which a halo shape pattern appears in analysis of the electron diffraction pattern.

8. The semiconductor device according to claim 6, wherein the second insulating layer is a silicon oxide film which is obtained with a sputtering method.

9. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a first insulating layer over the gate electrode layer;

an oxide semiconductor layer including indium, gallium, and zinc over the first insulating layer;

a source electrode layer or a drain electrode layer over the oxide semiconductor layer; and

a second insulating layer which covers the source electrode layer or the drain electrode layer,

wherein the oxide semiconductor layer includes a region whose thickness is smaller than a thickness of a region which overlaps with the source electrode layer or the drain electrode layer,

wherein the second insulating layer is in contact with the region of the oxide semiconductor layer whose thickness is smaller, and

wherein the region of the oxide semiconductor layer whose thickness is smaller has an incubation state, which is neither a crystal state nor an amorphous state.

10. The semiconductor device according to claim 9, wherein the incubation state, the crystal state, or the amorphous state is analyzed by an electron diffraction pattern.

11. The semiconductor device according to claim 9,

wherein the incubation state is a state in which a spot thereof does not appear clearly but periodically in analysis of an electron diffraction pattern,

wherein the crystal state is a state in which a spot appears clearly in analysis of the electron diffraction pattern, and

wherein the amorphous state is a state in which a halo shape pattern appears in analysis of the electron diffraction pattern.

12. The semiconductor device according to claim 9, wherein the second insulating layer is a silicon oxide film which is obtained with a sputtering method.