SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE
First Claim
1. A semiconductor device comprising:
- a first memory cell; and
a second memory cell electrically connected to the first memory cell,wherein the first memory cell and the second memory cell each comprise;
a first transistor;
a second transistor electrically connected to the first transistor; and
a capacitor electrically connected to the first transistor and the second transistor,wherein the first transistor of the first memory cell further comprises;
an electrode;
an oxide semiconductor layer provided over the electrode;
a gate insulating layer over the oxide semiconductor layer; and
a first gate electrode over the gate insulating layer, andwherein the first transistor of the second memory cell further comprises;
the oxide semiconductor layer;
the gate insulating layer over the oxide semiconductor layer; and
a second gate electrode over the gate insulating layer.
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Accused Products
Abstract
A semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide-gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a ions time. Transistors each including an oxide semiconductor in memory cells of the semiconductor device are connected in series; thus, a source electrode of the transistor including an oxide semiconductor in the memory cell and a drain electrode of the transistor including an oxide semiconductor in the adjacent memory cell can be connected to each other. Therefore, the area occupied by the memory cells can be reduced.
126 Citations
17 Claims
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1. A semiconductor device comprising:
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a first memory cell; and a second memory cell electrically connected to the first memory cell, wherein the first memory cell and the second memory cell each comprise; a first transistor; a second transistor electrically connected to the first transistor; and a capacitor electrically connected to the first transistor and the second transistor, wherein the first transistor of the first memory cell further comprises; an electrode; an oxide semiconductor layer provided over the electrode; a gate insulating layer over the oxide semiconductor layer; and a first gate electrode over the gate insulating layer, and wherein the first transistor of the second memory cell further comprises; the oxide semiconductor layer; the gate insulating layer over the oxide semiconductor layer; and a second gate electrode over the gate insulating layer. - View Dependent Claims (2, 3)
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4. A semiconductor device comprising:
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a source line; a bit line; m (m is an integer greater than or equal to
2) signal lines;m word lines; a selection line; first to m-th memory cells connected in series between the source line and the bit line; and a selection transistor whose gate terminal is electrically connected to the selection line, wherein the first to m-th memory cells each comprise; a first transistor comprising a first gate terminal, a first source terminal, and a first drain terminal; a second transistor comprising a second gate terminal, a second source terminal, and a second drain terminal; and a capacitor, wherein the second transistor includes an oxide semiconductor layer, wherein the source line is electrically connected to the first source terminal in the m-th memory cell through the selection transistor, wherein the bit line is electrically connected to the second drain terminal in the first memory cell and is electrically connected to the first drain terminal in the first memory cell, wherein the k-th (k is a natural number greater than or equal to 1 and less than or equal to m) signal line is electrically connected to the second gate terminal in the k-th memory cell, wherein the k-th word line is electrically connected to one terminal of the capacitor in the k-th memory cell, wherein the second drain terminal in the l-th (l is a natural number greater than or equal to 2 and less than or equal to m) memory cell is electrically connected to the first gate terminal in the (l−
1)-th memory cell, the second source terminal in the (l−
1)-th memory cell, and the other terminal of the capacitor in the (l−
1)-th memory cell,wherein the first gate terminal in the m-th memory cell, the second source terminal, in the m-th memory cell, and the other terminal of the capacitor in the m-th memory cell are electrically connected to one another, and wherein the first drain terminal in the l-th memory cell is electrically connected to the first source terminal in the (l−
1)-th memory cell. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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11. A semiconductor device comprising:
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a source line; a bit line; m (m is an integer greater than or equal to
2) signal lines;m word lines; a first selection line; a second selection line; first to m-th memory cells connected in series between the source line and the bit line; a first selection transistor whose gate terminal is electrically connected to the first selection line; and a second selection transistor whose gate terminal is electrically connected to the second selection line, wherein the first to m-th memory cells each comprise; a first transistor comprising a first gate terminal, a first source terminal, and a first drain terminal; a second transistor comprising a second gate terminal, a second source terminal, and a second drain terminal; and a capacitor, wherein the second transistor includes an oxide semiconductor layer, wherein the source line is electrically connected to the first source terminal in the m-th memory cell through the second selection transistor, wherein the bit line is electrically connected to the second drain terminal in the first memory cell, and is electrically connected to the first drain terminal in the first memory cell through the first selection transistor, wherein the k-th (k is a natural number greater than or equal to 1 and less than or equal to m) signal line is electrically connected to the second gate terminal in the k-th memory cell, wherein the k-th word line is electrically connected to one terminal of the capacitor in the k-th memory cell, wherein the second drain terminal, in the l-th (l is a natural number greater than or equal to 2 and less than or equal to m) memory cell is electrically connected to the first gate terminal in the (l−
1)-th memory cell, the second source terminal in the (l−
1)-th memory cell, and the other terminal of the capacitor in the (l−
1)-th memory cell,wherein the first gate terminal in the m-th memory cell, the second source terminal in the m-th memory cell, and the other terminal of the capacitor in the m-th memory cell are electrically connected to one another, and wherein the first drain terminal in the l-th memory cell is electrically connected to the first source terminal in the (l−
1)-th memory cell. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification