SEMICONDUCTOR DEVICE

• US 20110227074A1
• Filed: 03/11/2011
• Published: 09/22/2011
• Est. Priority Date: 03/19/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KATO, Kiyoshi, NAGATSUKA, Shuhei
• Granted Patent: US 8,946,709 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved.

Claims

1. A semiconductor device comprising:

a memory cell comprising;

a first transistor comprising;

a first channel formation region;

a first gate insulating layer over the first channel formation region; and

a first gate electrode over the first gate insulating layer, the first gate electrode overlapping with the first channel formation region;

a second transistor over the first transistor, the second transistor comprising;

a second channel formation region;

a first electrode electrically connected to the second channel formation region;

a second gate electrode overlapping with the second channel formation region; and

a second gate insulating layer between the second channel formation region and the second gate electrode;

an insulating layer over the second transistor; and

a second electrode over the insulating layer, the second electrode overlapping with the first electrode,

wherein the first channel formation region and the second channel formation region comprise different semiconductor materials,

wherein the first gate electrode is electrically connected to the first electrode, and

wherein the first electrode overlaps with the first gate electrode.

2. The semiconductor device according to claim 1, wherein the second electrode overlaps with at least part of the second gate electrode with the insulating layer between the second electrode and the second gate electrode.

3. The semiconductor device according to claim 1,

wherein the second electrode overlaps with at least part of the first gate electrode.

4. The semiconductor device according to claim 1,

wherein the first transistor comprises impurity regions between which the first channel formation region is sandwiched.

5. The semiconductor device according to claim 1,

wherein the first channel formation region is formed in a single crystal silicon substrate.

6. The semiconductor device according to claim 1,

wherein the first channel formation region is formed in a semiconductor film over a substrate.

7. The semiconductor device according to claim 1,

wherein the second channel formation region of the second transistor comprises an oxide semiconductor.

8. A semiconductor device comprising:

a memory cell comprising;

a first channel formation region;

a first gate insulating layer over the first channel formation region;

a first gate electrode over the first gate insulating layer, the first gate electrode overlapping with the first channel formation region;

a first electrode over the first gate electrode;

a first semiconductor layer over the first electrode, the first semiconductor layer comprising a second channel formation region;

a second gate insulating layer over the first semiconductor layer;

a second gate electrode over the second gate insulating layer, the second gate electrode overlapping with the second channel formation region;

an insulating layer over the second gate electrode; and

a second electrode over the insulating layer, the second electrode overlapping with the first electrode.

9. The semiconductor device according to claim 8, wherein the second electrode overlaps with at least part of the second gate electrode with the insulating layer between the second electrode and the second gate electrode.

10. The semiconductor device according to claim 8,

wherein the second electrode overlaps with at least part of the first gate electrode.

11. The semiconductor device according to claim 8,

wherein the first channel formation region is formed in a single crystal silicon substrate.

12. The semiconductor device according to claim 8,

wherein the first channel formation region is formed in a semiconductor film over a substrate.

13. The semiconductor device according to claim 8,

wherein the second channel formation region comprises an oxide semiconductor.