3D INTEGRATED CIRCUIT STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

• US 20110227158A1
• Filed: 06/22/2010
• Published: 09/22/2011
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Zhu, Huilong
• Granted Patent: US 9,064,849 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention discloses a semiconductor device. In one embodiment, the semiconductor device comprises a substrate, a diffusion stop layer formed on the substrate, an SOI layer formed on the diffusion stop layer, an MOSFET transistor formed on the SOI layer, and a TSV formed in a manner of penetrating through the substrate, the diffusion stop layer, the SOI layer, and a layer where the MOSFET transistor is located; and an interconnect structure connecting the MOSFET transistor and the TSV.

Claims

1. A three-dimension integrated circuit structure, characterized in that the integrated circuit structure comprises:

a first wafer, comprising;

a substrate;

a diffusion stop layer formed on the substrate;

a silicon-on-insulator (SOI) layer formed on the diffusion stop layer;

a metal oxide semiconductor field effect transistor (MOSFET) formed on the SOI layer;

a through-silicon-via (TSV) formed in a manner of penetrating through the substrate, the stop diffusion layer, the SOI layer and a layer where the MOSFET transistor is located; and

a first interconnect structure for connecting the MOSFET transistor and the TSV;

wherein the bottom of the first wafer is ground to expose the TSV filled with a metal material, and the bottom of the first wafer is connected to external circuits or a second interconnect structure of a second wafer by means of the TSV.

2. The integrated circuit structure according to claim 1, characterized in that the diffusion stop layer is formed of nitride.

3. The integrated circuit structure according to claim 2, characterized in that the nitride comprises Si₃N₄ or SiCN.

4. The integrated circuit structure according to claim 1, characterized in that the first wafer further comprises a first oxide layer formed between the substrate and the diffusion stop layer.

5. The integrated circuit structure according to claim 1, characterized in that the first wafer further comprises a second oxide layer formed between the diffusion stop layer and the SOI layer.

6. The integrated circuit structure according to claim 1, characterized in that the TSV further comprises a buried layer deposited before filling the metal material.

7. The integrated circuit structure according to claim 6, characterized in that the buried layer comprises at least a material selected from a group comprising Ru, Ta, TaN, Ti, TiN, TaSiN, TiSiN, TiW and WN.

8. A method of forming a three-dimension integrated circuit, characterized in that the method further comprises steps of:

forming a first wafer, wherein forming the first wafer comprises;

forming a substrate;

forming a diffusion stop layer on the substrate;

forming an SOI layer on the diffusion stop layer;

forming an MOSFET transistor on the SOI layer;

forming a TSV in a manner of penetrating through the substrate, the stop diffusion layer, the SOI layer and a layer where the MOSFET transistor is located; and

forming an interconnect structure for connecting the MOSFET transistor and the TSV;

grinding the bottom of the first wafer to expose the TSV filled with a metal material; and

connecting the bottom of the first wafer to external circuits or an interconnect structure of a second wafer by means of the TSV.

9. The method according to claim 8, characterized in that the diffusion stop layer is formed of nitride.

10. The method according to claim 9, characterized in that the nitride comprises Si₃N₄ or SiCN.

11. The method according to claim 8, characterized by further comprising a step of forming a first oxide layer between the substrate and the diffusion stop layer.

12. The method according to claim 8, characterized by further comprising a step of forming a second oxide layer between the diffusion stop layer and the SOI layer.

13. The method according to claim 8, characterized by further comprising a step of depositing a buried layer in the TSV before filling the metal material into the TSV.

14. The method according to claim 13, characterized in that the buried layer comprises at least a material selected from a group comprising Ru, Ta, TaN, Ti, TiN, TaSiN, TiSiN, TiW and WN.

15. A semiconductor device, characterized in that the semiconductor device comprises:

a substrate;

a diffusion stop layer formed on the substrate;

an SOI layer formed on the diffusion stop layer;

an MOSFET transistor formed on the SOI layer;

a TSV formed in a manner of penetrating through the substrate, the stop diffusion layer, the SOI layer and a layer where the MOSFET transistor is located; and

an interconnect structure for connecting the MOSFET transistor and the TSV.

16. The semiconductor device according to claim 15, characterized in that the diffusion stop layer is formed of nitride.

17. The semiconductor device according to claim 16, characterized in that the nitride comprises Si₃N₄ or SiCN.

18. The semiconductor device according to claim 15, characterized by further comprising a first oxide layer formed between the substrate and the diffusion stop layer.

19. The semiconductor device according to claim 15, characterized by further comprising a second oxide layer formed between the diffusion stop layer and the SOI layer.

20. The semiconductor device according to claim 15, characterized in that the TSV further comprises a buried layer deposited before filling the metal material.