STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING

• US 20110227166A1
• Filed: 06/01/2011
• Published: 09/22/2011
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: VOLDMAN, Steven H.
• Granted Patent: US 8,390,074 B2
• Time in Patent Office: Days
• US Class Current: 257/372
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.

Claims

1. A structure, comprising:

a latchup sensitive structure; and

a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.

2. The structure of claim 1, wherein the latchup sensitive structure is a P+ diffusion structure.

3. The structure of claim 1, wherein the latchup sensitive structure is a CMOS structure.

4. The structure of claim 1, wherein the latchup sensitive structure is an N+ diffusion structure.

5. The structure of claim 1, wherein the through wafer via isolates the latchup sensitive structure from an external source.

6. The structure of claim 1, wherein the through wafer via is filled with one of:

a refractory material, a metal, an insulator and a metal material lined with an insulator.

7. The structure of claim 1, wherein the through wafer via completely surrounds the latchup sensitive structure.

8. The structure of claim 1, wherein the through wafer via partially surrounds the latchup sensitive structure.

9. The structure of claim 1, wherein the through wafer via is a guard ring structure that prevents latchup resulting from a minority injection source.

10. The structure of claim 1, wherein:

a latchup sensitive structure in a substrate;

the trough via through is provided on an underside of the substrate and adjacent the latchup sensitive structure to isolate the latchup sensitive structure from at least an external source.

11. The structure of claim 10, wherein the trough via is filled with a metal material, refractory material, an insulator, or a metal material with an insulator liner.

12. The structure of claim 10, wherein the latchup sensitive structure is one of:

a P+ diffusion structure, a CMOS structure and a N+ diffusion structure.

13. The structure of claim 10, wherein the latchup sensitive structure is bounded by the through wafer via to prevent parasitic carriers from being injected into the latchup sensitive structure.

14. The structure of claim 10, wherein the through wafer via is entirely surrounding the latchup sensitive structure.

15. A structure comprising:

a latchup sensitive structure; and

a guard ring that bounds the latchup sensitive structure to isolate the latchup sensitive structure from an external source.

16. The structure of claim 15, wherein the latchup sensitive structure is one of a CMOS, PMOS and NMOS device.

17. The structure of claim 15, wherein the guard ring is one of a metal material, a refractory material, an insulator, a metal lined with an insulator or devoid of material.

18. The structure of claim 15, wherein the guard ring completely surrounds the latchup sensitive structure.

19. The structure of claim 15, wherein the guard ring is structured to protect the latchup sensitive structure from a high voltage external source.

20. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a latchup sensitive structure, and a guard ring that bounds the latchup sensitive structure to isolate the latchup sensitive structure from an external source.