SEMICONDUCTOR MEMORY DEVICE

• US 20110228584A1
• Filed: 03/14/2011
• Published: 09/22/2011
• Est. Priority Date: 03/19/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Granted Patent: US 8,487,303 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

In a matrix including a plurality of memory cells, each in which a drain of a writing transistor is connected to a gate of a reading transistor and the drain is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line, a source of the writing transistor and a source of the reading transistor is connected to a bit line, and a drain of the reading transistor is connected to a reading word line. A conductivity type of the writing transistor is different from a conductivity type of the reading transistor. In order to increase the integration degree, a bias line may be substituted with a reading word line in another row, or memory cells are connected in series so as to have a NAND structure, and a reading word line and a writing word line may be shared.

Claims

1. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a memory cell,

wherein the first to third wirings are parallel to one another and the first wiring and the fourth wiring intersect with each other,

wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein a source of the first transistor and a source of the second transistor are connected to the fourth wiring,

wherein a drain of the second transistor is connected to the third wiring, and

wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor.

6. The semiconductor memory device according to claim 1, wherein the conductivity type of the second transistor is p-type.

11. The semiconductor memory device according to claim 1, wherein the first transistor comprises an oxide semiconductor.

16. The semiconductor memory device according to claim 1, wherein the second transistor comprises a single crystal silicon semiconductor.

2. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring;

a first memory cell; and

a second memory cell,

wherein the first to third wirings are parallel to one another,

wherein the first wiring and the fourth wiring intersect with each other,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein a source of the first transistor and a source of the second transistor are connected to the fourth wiring,

wherein a drain of the second transistor is connected to the third wiring,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a gate of the third transistor is connected to the third wiring, wherein a source of the third transistor and a source of the fourth transistor are connected to the fourth wiring, and

wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor.

7. The semiconductor memory device according to claim 2, wherein the conductivity type of the second transistor is p-type.

12. The semiconductor memory device according to claim 2, wherein each of the first transistor and the third transistor comprises an oxide semiconductor.

17. The semiconductor memory device according to claim 2, wherein each of the second transistor and the fourth transistor comprises a single crystal silicon semiconductor.

3. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring;

a fifth wiring;

a sixth wiring;

a first memory cell; and

a second memory cell,

wherein the first to fifth wirings are parallel to one another,

wherein the first wiring and the sixth wiring intersect with each other,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein a gate of the third transistor is connected to the third wiring,

wherein the other electrode of the second capacitor is connected to the fourth wiring,

wherein a drain of the second transistor and a drain of the fourth transistor are connected to the fifth wiring,

wherein a source of the first transistor, a source of the second transistor, a source of the third transistor, and a source of the fourth transistor are connected to the sixth wiring, and

wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor.

8. The semiconductor memory device according to claim 3, wherein the conductivity type of the second transistor is p-type.

13. The semiconductor memory device according to claim 3, wherein each of the first transistor and the third transistor comprises an oxide semiconductor.

18. The semiconductor memory device according to claim 3, wherein each of the second transistor and the fourth transistor comprises a single crystal silicon semiconductor.

4. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring;

a fifth wiring; and

a memory unit comprising a first memory cell and a second memory cell,

wherein the first to fourth wirings are parallel to one another,

wherein the first wiring and the fifth wiring intersect with each other,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein a gate of the third transistor is connected to the third wiring,

wherein the other electrode of the second capacitor is connected to the fourth wiring,

wherein a drain of the second transistor is connected to a source of the fourth transistor,

wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor,

wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and

wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.

9. The semiconductor memory device according to claim 4, wherein the conductivity type of the second transistor is p-type.

14. The semiconductor memory device according to claim 4, wherein each of the first transistor and the third transistor comprises an oxide semiconductor.

19. The semiconductor memory device according to claim 4, wherein each of the second transistor and the fourth transistor comprises a single crystal silicon semiconductor.

5. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a memory unit comprising a first memory cell and a second memory cell,

wherein the first to third wirings are parallel to each other,

wherein the first wiring and the fourth wiring intersect with each other,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor and a gate of the third transistor are connected to the second wiring,

wherein the other electrode of the second capacitor is connected to the third wiring,

wherein a drain of the second transistor is connected to a source of the fourth transistor,

wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor,

wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and

wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.

10. The semiconductor memory device according to claim 5, wherein the conductivity type of the second transistor is p-type.

15. The semiconductor memory device according to claim 5, wherein each of the first transistor and the third transistor comprises an oxide semiconductor.

20. The semiconductor memory device according to claim 5, wherein each of the second transistor and the fourth transistor comprises a single crystal silicon semiconductor.