MLC SELF-RAID FLASH DATA PROTECTION SCHEME

• US 20110228601A1
• Filed: 03/17/2010
• Published: 09/22/2011
• Est. Priority Date: 03/17/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Prins, Doug, Olbrich, Aaron K.
• Granted Patent: US 8,365,041 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Claims

1. A method of managing a multiple level cell flash memory that is logically organized to include a block having a plurality of pages, each page including a plurality of sectors, the method comprising:

(a) choosing a parity sector in each page;

(b) assigning the pages of the block into one or more groups and selecting a parity page in each group;

(c) for each page, calculating a sector parity value for data stored in the sectors of the page and storing the sector parity value into the parity sector of the page; and

(d) calculating a group parity value of data stored in the pages of the group and storing the group parity value in the parity page.

2. The method of managing flash memory as in claim 1, further comprising:

(e) repeating steps (c) and (d) for each group.

3. The method of managing flash memory as in claim 2, wherein the sectors of each page are each assigned a sector number, the method further comprising:

(f) selecting a column parity page and calculating, for each sector number, a column parity for all sectors of the sector number in the pages of the block.

4. The method as in claim 1, wherein each multiple level cell is shared by at least two pages of the block.

5. The method as in claim 1, wherein each group consists of 8 pages.

6. The method as in claim 4, wherein the pages sharing each multiple level cells are assigned to different groups.

7. The method as in claim 6, wherein the groups are each assigned a group number and wherein the pages sharing a multiple level cell are assigned consecutive group numbers.

8. The method as in claim 7, wherein one or more of the groups are assigned half the number of pages as assigned to each of the remainder of the groups of the block.

19. A flash memory data storage system operable in accordance with the method of claim 1.

9. A method of managing a multiple level cell flash memory that is organized logically into one or more blocks each having a plurality of pages, each page including a plurality of sectors, the method comprising:

(a) selecting from the blocks a parity block;

(b) choosing a parity sector in each page;

(c) assigning the pages of the block into a plurality of groups;

(d) for each page, calculating a sector parity value for data stored in the sectors in each page and storing the sector parity value in the parity sector;

(e) prior to completing data writing into all pages of a group, calculating a subset group parity for a subset of pages in the group; and

(f) storing the subset group parity in the parity block.

10. The method as in claim 9, further comprising the steps of:

(h) repeating steps (d) to (f).

11. The method as in claim 9, wherein the sectors of each page are each assigned a sector number, the method further comprising:

(f) selecting a column parity page and calculating, for each sector number, a column parity for all sectors of the sector number in the pages of the block.

13. The method as in claim 9, wherein each group consists of 8 pages.

The method as in claim 9, wherein each multiple level cell is shared by two pages of the same group.

14. The method as in claim 9, wherein the parity block resides outside the flash memory.

15. The method as in claim 9, wherein the parity block resides on a non-volatile memory.

16. The method as in claim 9, wherein the subset group parity of a group written into the parity block is erased after data is completely written into the pages of the group.

17. The method as in claim 9, the subset group parity of a group written into the parity block is saved after data is completely written into the pages of the group.

18. The method as in claim 9, wherein the subset group parity is calculated from data in half of the pages of the group.

20. A flash memory data storage system operable in accordance with the method of claim 9.

21. A method of managing a multiple level cell flash memory that is organized logically into blocks each including a plurality of pages, each page including a plurality of sequentially numbered sectors, the method comprising:

(a) programming and erasing data on a page at a predetermined speed;

(b) detecting an error rate for each page of a block and identifying a group of high error pages based on the error rates; and

(c) applying a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.

22. A method of managing a multiple level cell flash memory that includes a sense circuitry, comprising:

(a) detecting charge levels of the multiple level cells using a first sense voltage, and compiling a first correlation table between the first sense voltage and each of the charge level of each of the multiple level cell;

(b) selecting a second sense voltage that is lower than the first sense voltage and detecting charge levels of the multiple level cells using the second sense voltage, and compiling a correlation table between the second sense voltage and each of the charge level of each of the multiple level cells;

(c) replace the first correlation table by the second correlation table.