STACKED PACKAGES WITH BRIDGING TRACES

• US 20110230013A1
• Filed: 05/25/2011
• Published: 09/22/2011
• Est. Priority Date: 12/28/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem
• Granted Patent: US 8,349,654 B2
• Time in Patent Office: Days
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]

Abstract

A microelectronic assembly that includes a first microelectronic element having a first rear surface. The assembly further includes a second microelectronic element having a second rear surface. The second microelectronic element is attached to the first microelectronic element so as to form a stacked package. A bridging element electrically connects the first microelectronic element and the second microelectronic element. The first rear surface of the first microelectronic element faces toward the second rear surface of the second microelectronic element.

Claims

1. A method of assembling a stacked microelectronic assembly comprising the steps of:

forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, wherein the rear faces of the first subassembly and second subassembly confront one another;

electrically connecting a plurality of contacts exposed at a front face of the first subassembly to a plurality of contacts exposed at a front face of the second subassembly.

2. The method of claim 1 wherein the first subassembly and second subassembly each include saw lanes that are aligned during the step of forming the microelectronic assembly.

3. The method of claim 2, further comprising dicing through the saw lanes of the first and second subassemblies so as so form individual stacked units, wherein at least some of the plurality of microelectronic elements of the first subassembly and the second subassembly have traces that extend from respective contacts to the saw lanes of the respective first and second subassemblies such that after the dicing step the traces are exposed.

4. The method of claim 3, wherein the step of electrically connecting the plurality of contacts of the first subassembly to the contacts of the second subassembly includes forming bridging elements between the traces of the first subassembly and second subassembly.

5. The method of claim 4, wherein the bridging elements are disposed on the edges of the microelectronic elements of both the first subassembly and second subassembly.

6. A method of assembling a stacked package comprising the steps of forming a first individual stacked unit and a second individual stacked unit according to claim 4, further comprising electrically connecting at least some of the contacts of the first individual stacked unit to at least some of the contacts of the second individual stacked unit.

7. The method of claim 1, further comprising forming a plurality of vias in both the first subassembly and second subassembly, wherein the plurality of vias extend from the rear faces of the first and second subassemblies to the front faces of both the subassemblies and are aligned with the contacts of the first and second subassemblies so as to expose the contacts to the rear faces of the respective subassembly.

8. The method of claim 7, wherein a conductive material is deposited into the plurality of traces.

9. The method of claim 8, wherein prior to forming a microelectronic assembly, the conductive material in the plurality of vias of the first subassembly is aligned with the conductive material in the plurality of vias of the second assembly.

10. The method of claim 9, wherein the step of electrically connecting the contacts of the first subassembly to the contacts of the second subassembly includes electrically connecting the conductive material disposed in the plurality of vias of the first subassembly to the conductive material in the plurality of vias of the second subassembly.

11. The method of claim of claim 10, further comprising dicing the microelectronic assembly at predetermined locations to form individual stacked units.