SYSTEM FOR MEMORY INSTANTIATION AND MANAGEMENT

• US 20110231628A1
• Filed: 06/29/2010
• Published: 09/22/2011
• Est. Priority Date: 03/16/2010
• Status: Abandoned Application

• Current Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Inventors: Gelter, Aaron, Parker, Brian, Boatright, Robert
• Application Number:
  US12/826,419
• Publication Number:
  US 20110231628A1
• Time in Patent Office: Days
• US Class Current: 711/171
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A system for memory instantiation in a programmable logic device (PLD) includes a computing device having a processor and memory coupled with the PLD. The processor is configured to receive memory parameters including at least a data width and a data depth. The processor is also configured to determine a number and sizes of block random access memory (BRAM) primitives required for data storage based on the memory parameters and based on one or more sizes of BRAM primitives available on the programmable logic device. In one example, the processor minimizes a size of the total number of BRAMs required for instantiation on the PLD. The processor is also configured to instantiate the determined number and corresponding sizes of the BRAM primitives in logic for configuration of the programmable logic device to include a device memory within the available BRAM primitives thereof corresponding to the determined number and sizes of the BRAM primitives.

Claims

1. A system for memory instantiation in a programmable logic device, the system comprising:

a computing device having a processor and memory coupled with the programmable logic device, the processor configured to;

receive a plurality of memory parameters including at least a data width and a data depth, where an address width is derivable from the data depth;

determine a number and sizes of block random access memory (BRAM) primitives required for data storage based on the plurality of memory parameters and based on one or more sizes of a plurality of BRAM primitives available on the programmable logic device; and

instantiate the determined number and corresponding sizes of the BRAM primitives in logic for configuration of the programmable logic device to include a device memory within the available BRAM primitives thereof corresponding to the determined number and sizes of the BRAM primitives.

2. The system of claim 1, where the processor is configured to minimize a size of the determined number of BRAMs on the programmable logic device based on the plurality of memory parameters.

3. The system of claim 1, where two or more BRAM primitives of one or more predetermined sizes are determined as required and the processor is further configured to:

instantiate, in logic, address and data multiplexing between the two or more BRAM primitives; and

send compiled logic for the address and data multiplexing along with the determined number and sizes of the BRAM primitives to the programmable logic device.

4. The system of claim 3, where the programmable logic device configures the two or more BRAM primitives and data multiplexing based on the compiled logic received from the computing device.

5. The system of claim 3, where the BRAM primitives each require a predetermined number of bits for addressing depending on an architecture of the programmable logic device, the processor configured to select one or more of a plurality of upper bits that exist beyond the predetermined number of bits with which to multiplex for address selection between the two or more BRAMs.

6. The system of claim 3, where the processor is configured to create busses to support data and parity ports specified by the BRAM primitives.

7. The system of claim 3, where the processor is configured to execute a constant function from within a port list of the programmable logic device, the constant function providing a bus width of a port based on the address width.

8. The system of claim 1, where the plurality of memory parameters comprise parameters derived from global design parameters, which are selected based on a device or system in which the programmable logic device will be a part.

9. The system of claim 1, where the plurality of memory parameters include default parameters used by the processor when specific ones of the plurality of memory parameters are not specified by a user.

10. The system of claim 1, where the plurality of memory parameters further comprise an architecture of the programmable logic device.

11. A method for memory instantiation and management in a programmable logic device executable by a computing device having a memory and processor coupled with the programmable logic device, the method comprising:

receiving, by the computing device, a plurality of memory parameters including at least a data width and a data depth;

determining, by the processor, a number and sizes of block random access memory (BRAM) primitives required for data storage based on the plurality of memory parameters and based on one or more sizes of a plurality of BRAM primitives available on the programmable logic device; and

instantiate, by the computing device, the determined number and corresponding sizes of the BRAM primitives in logic for configuration of the programmable logic device to include a device memory within the available BRAM primitives thereof corresponding to the determined number and sizes of the BRAM primitives.

12. The method of claim 11, further comprising the processor minimizing a size of the determined number of BRAMs on the programmable logic device based on the plurality of memory parameters.

13. The method of claim 11, where two or more BRAM primitives of one or more predetermined sizes are determined as required, further comprising the processor:

instantiating, in logic, address and data multiplexing between the two or more BRAM primitives; and

sending compiled logic for the address and data multiplexing along with the determined number and sizes of the BRAM primitives to the programmable logic device.

14. The method of claim 13, where the programmable logic device configures the two or more BRAM primitives based on the compiled logic received from the computing device.

15. The method of claim 13, where the BRAM primitives each require a predetermined number of bits for addressing depending on an architecture of the programmable logic device, the method further comprising the processor:

selecting one or more of a plurality of upper bits that exist beyond the predetermined number of bits with which to multiplex for address selection between the two or more BRAMs.

16. The method of claim 13, further comprising the processor creating busses to support data and parity ports specified by the BRAM primitives.

17. The method of claim 13, further comprising the processor executing a constant function from within a port list of the programmable logic device, the constant function providing a bus width of a port based on an address width derivable from the data depth.

18. The method of claim 11, where the plurality of memory parameters comprise parameters derived from global design parameters, which are selected based on a device or system in which the programmable logic device will be a part.

19. The method of claim 11, where the plurality of memory parameters include default parameters used by the processor when specific ones of the plurality of memory parameters are not specified by a user.

20. The method of claim 11, where the plurality of memory parameters further comprise an architecture of the programmable logic device.

21. A computer-readable storage medium comprising a set of instructions for instantiating and managing memory in a programmable logic device, the set of instructions executable by a computing device having a processor and memory, the computer-readable medium comprising:

instructions to receive a plurality of memory parameters including at least a data width and a data depth, where an address width is derivable from the data depth, in response to signals representative of user inputs through a user interface to input one or more local and global design parameters;

instructions to direct the processor to determine a number and sizes of block random access memory (BRAM) primitives required for data storage based on the plurality of memory parameters and based on one or more sizes of a plurality of BRAM primitives available on the programmable logic device; and

instructions to direct the processor to instantiate the determined number and corresponding sizes of the BRAM primitives in logic for configuration of the programmable logic device to include a device memory within the available BRAM primitives thereof corresponding to the determined number and sizes of the BRAM primitives.

22. The computer-readable storage medium of claim 21, further comprising:

instructions to direct the processor to minimize a size of the determined number of BRAMs on the programmable logic device based on the plurality of memory parameters.

23. The computer-readable storage medium of claim 21, where two or more BRAM primitives of one or more predetermined sizes are determined as required, further comprising:

instructions to direct the processor to instantiate, in logic, address and data multiplexing between the two or more BRAM primitives; and

instructions to direct the processor to send compiled logic for the address and data multiplexing along with the determined number and sizes of the BRAM primitives to the programmable logic device.

24. The computer-readable storage medium of claim 23, where the programmable logic device configures the two or more BRAM primitives based on the compiled logic received from the computing device.

25. The computer-readable storage medium of claim 23, where the BRAM primitives each require a predetermined number of bits for addressing depending on an architecture of the programmable logic device, further comprising:

instructions to direct the processor to select one or more of a plurality of upper bits that exist beyond the predetermined number of bits with which to multiplex for address selection between the two or more BRAMs.

26. The computer-readable storage medium of claim 23, further comprising:

instructions to direct the processor to create busses to support data and parity ports specified by the BRAM primitives.

27. The computer-readable storage medium of claim 23, further comprising:

instructions to direct the processor to execute a constant function from within a port list of the programmable logic device, the constant function providing a bus width of a port based on the address width.

28. The computer-readable storage medium of claim 21, where the plurality of memory parameters comprise parameters derived from the global design parameters, which are selected based on a device or system in which the programmable logic device will be a part.

29. The computer-readable storage medium of claim 21, where the plurality of memory parameters include default parameters used by the processor when specific ones of the plurality of memory parameters are not specified by a user.

30. A system for memory instantiation and management in a programmable logic device, the system comprising:

a computing device having a processor and memory coupled with the programmable logic device;

a user interface coupled with the processor configured to receive a plurality of memory parameters including at least a data width and a data depth, where an address width is derivable from the data depth;

an electronic circuit design tool coupled with the processor and the programmable logic device configured to determine a number and sizes of block random access memory (BRAM) primitives required for data storage based on the plurality of memory parameters and based on an architecture of the programmable logic device; and

the electronic circuit design tool further configured to instantiate the determined number and corresponding sizes of the BRAM primitives in logic for configuration of the programmable logic device such as to minimize a total size of the determined number of BRAMs to be formed on the programmable logic device.

31. The system of claim 30, where two or more BRAM primitives of one or more predetermined sizes are determined as required, where the electronic circuit design tool is further configured to:

instantiate, in logic, address and data multiplexing between the two or more BRAM primitives; and

configure the address and data multiplexing within the programmable logic device for the two or more BRAM primitives, as interconnected.

32. The system of claim 31, where the BRAM primitives each require a predetermined number of bits for addressing depending on the architecture of the programmable logic device, where the electronic circuit design tool is further configured to:

select one or more of a plurality of upper bits that exist beyond the predetermined number of bits with which to multiplex for address selection between the two or more BRAMs.

33. The system of claim 30, where the plurality of memory parameters include one or more sizes of a plurality of BRAM primitives available on the programmable logic device.

34. The system of claim 30, where the plurality of memory parameters include default parameters used by the system when specific ones of the plurality of memory parameters are not specified by a user.