VERTICAL INTEGRATED SILICON NANOWIRE FIELD EFFECT TRANSISTORS AND METHODS OF FABRICATION

• US 20110233512A1
• Filed: 01/16/2008
• Published: 09/29/2011
• Est. Priority Date: 08/16/2005
• Status: Abandoned Application

• Current Assignee: California Polytechnic State University (California State University System)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: He, Rongrui, Goldberger, Joshua, Hochbaum, Allon, Yang, Peidong, Fan, Rong
• Application Number:
  US12/015,044
• Publication Number:
  US 20110233512A1
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Vertical integrated field effect transistor circuits and methods are described which are fabricated from Silicon, Germanium, or a combination Silicon and Germanium based on nanowires grown in place on the substrate. By way of example, vertical integrated transistors are formed from one or more nanowires which have been insulated, had a gate deposited thereon, and to which a drain is coupled to the exposed tips of one or more of the nanowires. The nanowires are preferably grown over a surface or according to a desired pattern in response to dispersing metal nanoclusters over the desired portions of the substrate. In one preferred implementation, SiCl₄ is utilized as a gas phase precursor during the nanowire growth process. In place nanowire growth is also taught in conjunction with structures, such as trenches, while bridging forms of nanowires are also described.

Claims

1. A field effect transistor, comprising:

a nanowire extending from a substrate base;

a dielectric material surrounding at least a portion of said nanowire;

a gate material surrounding at least a portion of said dielectric material;

said nanowire having an exposed tip, which is not covered with said dielectric material or said gate material; and

a drain material coupled to in contact with said exposed tip of said nanowire.

2. A field effect transistor as recited in claim 1, wherein a plurality of said nanowires extending from said substrate base are coupled to said drain material of a single drain contact pad.

3. A field effect transistor as recited in claim 1, wherein said nanowire extends substantially vertically from a horizontal substrate.

4. A field effect transistor as recited in claim 1, wherein said nanowire is grown from said substrate base.

5. A field effect transistor as recited in claim 4, wherein the growth orientation of said nanowire is controlled utilizing epitaxial crystal growth techniques.

6. A field effect transistor as recited in claim 4, wherein said nanowire is grown from Si or SiGe with any desired type and level of dopants.

7. A field effect transistor as recited in claim 1, wherein said nanowire is grown according to a vapor-liquid-solid (VLS) process.

8. A field effect transistor as recited in claim 7, wherein epitaxial crystal growth is used to grow the nanowire according to a vapor-liquid-solid epitaxy (VLSE) process.

9. A field effect transistor as recited in claim 7, wherein SiCl₄ is utilized as a gas phase precursor, without separately incorporating HCl gas, during growing of said nanowire.

10. A field effect transistor as recited in claim 7, wherein the material or dopant properties may be varied during nanowire growth to form a longitudinally patterned nanowire.

11. A field effect transistor as recited in claim 1, wherein the nanowire diameter is controlled in response to the diameter of an alloy droplet during nanowire growth from the substrate.

12. A field effect transistor as recited in claim 11, wherein a plurality of said alloy droplets are contained within a colloidal metal which is dispersed on the surface of said substrate prior to growth of a plurality of said nanowires.

13. A field effect transistor as recited in claim 12, wherein said colloidal metal comprises gold (Au).

14. A field effect transistor as recited in claim 1, wherein a plurality of said nanowires are grown on said substrate at sites of alloy droplets distributed across at least a portion of the substrate surface as monodispersed metal nanoclusters.

15. A field effect transistor as recited in claim 14:

wherein said substrate is patterned for growing nanowires in a pattern upon selected areas; and

wherein said pattern contains said monodispersed metal nanoclusters selectively disposed on said substrate from which said nanowires are grown.

16. A field effect transistor as recited in claim 15, wherein said substrate is patterned utilizing micro-contact printing.

17. A field effect transistor as recited in claim 1, wherein said field effect transistor comprises a vertical integrated nanowire field-effect transistor which is configured for integration within an electrical device, circuit or system.

18. A field effect transistor, comprising:

a plurality of nanowires grown from a substrate base;

said nanowires are grown utilizing SiCl₄ as a gas phase precursor;

a dielectric material surrounding at least a portion of each of said nanowires;

a gate material surrounding at least a portion of said dielectric material on each of said nanowires;

wherein each of said nanowires has an exposed tip, which is not covered with said dielectric material or said gate material; and

a drain material in contact with said exposed tip of each of said nanowires.

19. A method of fabricating a vertical integrated nanowire field effect transistor, comprising:

growing a nanowire vertically in-place on a substrate;

etching away nanoparticle catalysts;

forming a gate dielectric of a desired thickness;

depositing a gate metal on the nanowire to achieve a conformal coating;

depositing a dielectric onto the substrate;

etching undesired gate metal wherein the nanowire has an uncoated tip;

depositing a dielectric onto the substrate to electrically isolate the gate and drain materials; and

forming a drain pad in contact with said uncoated tip of said nanowire.

20. A method as recited in claim 19, wherein growing of said nanowires comprises:

dispersing metal nanoclusters of a desired diameter over one or more portions of the substrate, or within a pattern; and

epitaxially growing said nanowire from Si to a desired length utilizing SiCl₄ as a gas phase precursor.