SEMICONDUCTOR DEVICE

• US 20110233555A1
• Filed: 03/14/2011
• Published: 09/29/2011
• Est. Priority Date: 03/26/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami
• Granted Patent: US 9,040,980 B2
• Time in Patent Office: Days
• US Class Current: 257/60
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer.

Claims

1. A transistor comprising:

a source electrode layer;

an oxide semiconductor layer in contact with the source electrode layer;

a drain electrode layer in contact with the oxide semiconductor layer;

a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and

a gate insulating layer in contact with an entire surface of the gate electrode layer,

wherein the gate insulating layer on a bottom surface side of the gate electrode layer is in contact with the source electrode layer, and

wherein the gate insulating layer on an upper surface side of the gate electrode layer is in contact with the oxide semiconductor layer.

2. The transistor according to claim 1, wherein the gate electrode layer is a pair of gate electrode layers which face each other with the oxide semiconductor layer interposed therebetween, and the gate insulating layer is a pair of gate insulating layers which face each other with the oxide semiconductor layer interposed therebetween.

3. The transistor according to claim 2, wherein a conductive layer covered with the oxide semiconductor layer is provided between the pair of the gate electrode layers and between the pair of the gate insulating layers.

4. The transistor according to claim 1,

wherein the gate electrode layer is a pair of gate electrode layers which face each other with the oxide semiconductor layer interposed therebetween and the gate insulating layer is a pair of gate insulating layers which face each other with the oxide semiconductor layer interposed therebetween, and

wherein a plurality of units in each of which the pair of the gate electrode layers face each other and the pair of the gate insulating layers face each other is provided.

5. The transistor according to claim 4, wherein a conductive layer covered with the oxide semiconductor layer is provided between the pair of the gate electrode layers and the pair of the gate insulating layers in each of the plurality of units.

6. The transistor according to claim 1, wherein the gate electrode layer and the gate insulating layer are provided in circular shapes so as to surround the oxide semiconductor layer.

7. The transistor according to claim 6, wherein a conductive layer covered with the oxide semiconductor layer is provided inside the gate electrode layer and the gate insulating layer.

8. A transistor comprising:

a source electrode layer;

an oxide semiconductor layer in contact with the source electrode layer;

a drain electrode layer in contact with the oxide semiconductor layer;

a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and

a gate insulating layer in contact with an entire surface of the gate electrode layer,

wherein the gate insulating layer on a bottom surface side and an upper surface side of the gate electrode layer is in contact with the oxide semiconductor layer.

9. The transistor according to claim 8, wherein the gate electrode layer is a pair of gate electrode layers which face each other with the oxide semiconductor layer interposed therebetween, and the gate insulating layer is a pair of gate insulating layers which face each other with the oxide semiconductor layer interposed therebetween.

10. The transistor according to claim 9, wherein a conductive layer covered with the oxide semiconductor layer is provided between the pair of the gate electrode layers and between the pair of the gate insulating layers.

11. The transistor according to claim 8,

wherein the gate electrode layer is a pair of gate electrode layers which face each other with the oxide semiconductor layer interposed therebetween and the gate insulating layer is a pair of gate insulating layers which face each other with the oxide semiconductor layer interposed therebetween, and

wherein a plurality of units in each of which the pair of the gate electrode layers face each other and the pair of the gate insulating layers face each other is provided.

12. The transistor according to claim 11, wherein a conductive layer covered with the oxide semiconductor layer is provided between the pair of the gate electrode layers and the pair of the gate insulating layers in each of the plurality of units.

13. The transistor according to claim 8, wherein the gate electrode layer and the gate insulating layer are provided in circular shapes so as to surround the oxide semiconductor layer.

14. The transistor according to claim 13, wherein a conductive layer covered with the oxide semiconductor layer is provided inside the gate electrode layer and the gate insulating layer.