Avalanche capability improvement in power semiconductor devices

• US 20110233606A1
• Filed: 03/26/2010
• Published: 09/29/2011
• Est. Priority Date: 03/26/2010
• Status: Active Grant

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Granted Patent: US 8,264,035 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Claims

1. A power semiconductor device comprising a plurality of trench MOSFETs, wherein each of said trench MOSFETs further comprising:

a substrate of a first conductivity type;

an epitaxial layer of said first conductivity type over said substrate, wherein said epitaxial layer having a lower doping concentration than said substrate;

a plurality of gate trenches extending into said epitaxial layer, wherein each of said gate trenches has a first insulation layer lining its inner surface and a doped poly-silicon layer thereon;

a body region of a second conductivity type surrounding sidewall of each of said gate trenches between every two adjacent of said gate trenches;

a source region of said first conductivity type near top surface of said body region, wherein said source region surrounds top portion of sidewall of each of said gate trenches, and has a higher doping concentration than said epitaxial layer;

a second insulation layer disposed over said epitaxial layer and covering outer surface of said doped poly-silicon layer;

a source-body contact trench locating between every two adjacent of said gate trenches, opened through said second insulation layer and said source region, and extended into said body region;

a body ohmic contact doped region of said second conductivity type formed within said body region, surrounding at least bottom of each said source-body contact trench and having a higher doping concentration than said body region;

at least an avalanche capability enhancement doped region of said second conductivity type disposed underneath each said body ohmic contact doped region, wherein said avalanche capability enhancement doped region has a higher doping concentration than said body region but a lower doping concentration than said body ohmic contact doped region;

a metal plug filling in each said source-body contact trench;

a source metal disposed covering top surface of said second insulation layer; and

a drain metal disposed on rear side of said substrate.

2. The power semiconductor device claim 1, wherein there is only one said avalanche capability enhancement doped region underneath each said body ohmic contact doped region, wherein said avalanche capability enhancement doped region is formed completely within said body region.

3. The power semiconductor power device of claim 1, wherein there is only one said avalanche capability enhancement doped region underneath each said body ohmic contact doped region, wherein said avalanche capability enhancement doped region is formed partially overlap with said body region and partially extending into said epitaxial layer but shallower than said gate trenches.

4. The power semiconductor power device of claim 1, wherein there are two said avalanche capability enhancement doped regions, one of which is formed overlap with said body region and partially extending into said epitaxial layer but shallower than said gate trenches, and another is formed within said body region.

5. The power semiconductor power device of claim 1, wherein there are multiple of said avalanche capability enhancement doped regions, one of which is formed overlap with said body region and partially extending into said epitaxial layer but shallower than said gate trenches, and others are formed within said body region.

6. The power semiconductor device of claim 1, wherein said doped poly-silicon layer protrudes out from each of said gate trenches and at least a portion of said doped poly-silicon is positioned higher than sidewall of each of said gate trenches.

7. The power semiconductor device of claim 1, wherein top surface of said doped poly-silicon layer is not higher than sidewall of each of said gate trenches.

8. The power semiconductor device of claim 1, wherein each said source-body contact trench has sidewalls with taper angle α

₁ within said source region, and has sidewalls with taper angle α

₂ in said body region with respect to top surface of said epitaxial layer, wherein said taper angle α

₁ is equal to or less than 90 degree and said taper angle α

₁ is equal to or greater than said taper angle α

₂.

9. The power semiconductor device of claim 1, wherein said metal plug is tungsten plug padded by a barrier layer of Ti/TiN or Co/TiN or Ta/TiN.

10. The power semiconductor device of claim 9, wherein said source metal is Cu alloys or Al alloys padded by a resistance-reduction layer of Ti or Ti/TiN which covering the top surface of said second insulation layer and each said tungsten plug.

11. The power semiconductor device of claim 1, wherein said metal plug is said source metal directly filling into each said source-body contact trench.

12. The power semiconductor device of claim 10, wherein said source metal is Cu alloys or Al alloys padded by a barrier layer of Ti/TiN or Co/TiN or Ta/TiN.

13. The power semiconductor device of claim 1, wherein said drain metal is Ti/Ni/Ag.

14. A power semiconductor device comprising a plurality of trench IGBTs, wherein each of said trench IGBTs further comprising:

a first epitaxial layer of a first conductivity type over a substrate of a second conductivity type;

a second epitaxial layer of said first conductivity type over said first epitaxial layer, wherein said second epitaxial layer has a lower doping concentration than said first epitaxial layer;

a plurality of gate trenches extending into said epitaxial layer, wherein each of said gate trenches has a first insulation layer lining its inner surface and a doped poly-silicon layer thereon;

a base region of said second conductivity type surrounding sidewall of each of said gate trenches between every two adjacent of said gate trenches;

an emitter region of said first conductivity type near top surface of said base region, wherein said emitter region surrounds top portion of sidewall of each of said gate trenches, and has a higher doping concentration than said second epitaxial layer;

a second insulation layer disposed over said second epitaxial layer and covering outer surface of said doped poly-silicon layer;

an emitter-base contact trench locating between every two adjacent of said gate trenches, opened through said second insulation layer and said emitter region, and extended into said base region;

a base ohmic contact doped region of said second conductivity type formed within said base region surrounding at least bottom of each said emitter-base contact trench and having a higher doping concentration than said base region;

at least an avalanche capability enhancement doped region of said second conductivity type underneath each said base ohmic contact doped region, wherein said avalanche capability enhancement doped region has a higher doping concentration than said base region but a lower doping concentration than said base ohmic contact doped region;

a metal plug filling in each said emitter-base contact trench;

an emitter metal disposed covering top surface of said second insulation layer; and

a collector metal disposed on rear side of said substrate.

15. The power semiconductor device claim 14, wherein there is only one said avalanche capability enhancement doped region underneath each said base ohmic contact doped region, wherein said avalanche capability enhancement doped region is formed completely within said base regions.

16. The power semiconductor power device of claim 14, wherein there is only one said avalanche capability enhancement doped region underneath each said base ohmic contact doped region, wherein said avalanche capability enhancement doped region is formed partially overlap with said base region and partially extending into said second epitaxial layer but shallower than said gate trenches.

17. The power semiconductor power device of claim 14, wherein there are two avalanche capability enhancement doped regions, and one of which is formed overlap with said base region and partially extending into said epitaxial layer but shallower than said gate trenches, and another is formed within said base region.

18. The power semiconductor power device of claim 14, wherein there are multiple of avalanche capability enhancement doped regions, and one of which is formed overlap with said base region and partially extending into said second epitaxial layer but shallower than said gate trenches;

and others are formed within said base region.

19. The power semiconductor device of claim 14, wherein said doped poly-silicon layer protrudes out from each of said gate trenches and at least a portion of said doped poly-silicon is positioned higher than sidewall of each of said gate trenches.

20. The power semiconductor device of claim 14, wherein top surface of said doped poly-silicon layer is not higher than sidewall of each of said gate trenches.

21. The power semiconductor device of claim 14, wherein each said emitter-base contact trench has sidewalls with taper angle α

₁ within said emitter region, and has sidewalls with taper angle α

₂ in said base region with respect to top surface of said second epitaxial layer, wherein said taper angle α

₁ is equal to or less than 90 degree and said taper angle α

₁ is equal to or greater than said taper angle α

₂.

22. The power semiconductor device of claim 14, wherein said metal plug is tungsten plug padded by a barrier layer of Ti/TiN or Co/TiN or Ta/TiN.

23. The power semiconductor device of claim 22, wherein said emitter metal is Cu alloys or Al alloys padded by a resistance-reduction layer of Ti or Ti/TiN which covering the top surface of said second insulation layer and each said tungsten plug.

24. The power semiconductor device of claim 14, wherein said metal plug is said emitter metal directly filling into each said emitter-base contact trench.

25. The power semiconductor device of claim 24, wherein said emitter metal is Cu alloys or Al alloys padded by a barrier layer of Ti/TiN or Co/TiN or Ta/TiN.

26. The power semiconductor device of claim 14, wherein said collector metal is Ti/Ni/Ag.

27. A method for manufacturing a power semiconductor device comprising the steps of:

forming a trench mask over top surface of an epitaxial layer, the trench mask having apertures defining location of a plurality of gate trenches;

etching through the apertures in the trench mask to form a plurality o gate trenches in the epitaxial layer;

removing the trench mask;

forming a first insulation layer on inner surface of said gate trenches;

depositing a gate conductive layer over said first insulation in said gate trenches and onto top surface of said epitaxial layer;

etching or CMP said gate conductive layer such that said gate conductive layer is removed away from the top surface of said epitaxial layer;

carrying out ion implantation with dopant type opposite to said epitaxial layer to form a plurality of first doped regions extending between every two adjacent of said gate trenches;

forming implantation mask over the top surface of said epitaxial layer, wherein the implantation mask has apertures defining location of a plurality of second doped regions in active area;

carrying out ion implantation with dopant type same as said epitaxial layer such that said second doped regions are formed near top surface of said first doped regions;

depositing a second insulation layer over the top surface of said epitaxial layer;

forming a contact mask over said second insulation layer, the contact mask having apertures defining location of a plurality of first-second-doped-regions contact trenches;

etching said second insulation layer and said epitaxial layer through the apertures in said contact mask such that the first-second-doped-regions contact trenches have sidewalls in said second doped regions with taper angle α

₁, and have sidewalls in said first doped regions with taper angle α

₂ with respect to top surface of said epitaxial layer, wherein α

₁ is equal to or less than 90 degree and is equal to or greater than α

₂;

carrying out ion implantation with dopant type opposite to said epitaxial layer to form a third doped region surrounding at least bottom of each of said first-second-doped-regions contact trenches within said first doped regions;

carrying out at least one ion implantation with dopant type opposite to said epitaxial layer to form at least a fourth doped region underneath said third doped region.

28. The method of claim 27 further comprising:

depositing a barrier layer of Ti/TiN or Co/TiN or Ta/Tin on inner surface of said first-second-doped-regions contact trenches;

forming tungsten plugs within each of said first-second-doped-regions contact trenches;

depositing a resistance-reduction layer of Ti or Ti/TiN over top surface of said second insulation layer and said tungsten plugs;

depositing front metal of Al alloys or Cu alloys onto said resistance-reduction layer;

grinding backside of said substrate and depositing back metal of Ni/Ti/Ag.

29. The method of claim 27 further comprising:

depositing a barrier layer of Ti/TiN or Co/TiN or Ta/Tin on inner surface of said first-second-doped-regions contact trenches and over top surface of said second insulation layer;

depositing front metal of Al alloys or Cu alloys filling into said first-second-doped-regions contact trenches and onto top surface of said second insulation layer;

grinding backside of said substrate and depositing back metal of Ni/Ti/Ag.

30. The method of claim 27 wherein said ion implantation for formation of at least one fourth doped region is carried out with energy ranging from 100 KeV to 300 KeV and with dose from 1E12 to 1E14 cm⁻

2.