Wafer Level Packaging Bond

• US 20110233621A1
• Filed: 03/23/2010
• Published: 09/29/2011
• Est. Priority Date: 03/23/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, H. T., Chao, Lan-Lin, Liu, Martin, Chu, Richard, Peng, Jung-Huei, Hsieh, Yuan-Chih, Tsai, Chia-Shiung, Cheng, Chun-Wen, Lin, Hung-Hua
• Granted Patent: US 8,647,962 B2
• Time in Patent Office: Days
• US Class Current: 257/254
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.

Claims

1. A method, comprising:

providing a first substrate including a first bonding layer, wherein the first bonding layer includes silicon;

providing a second substrate including a second bonding layer, wherein the second bonding layer includes aluminum; and

bonding the first substrate and the second substrate, wherein the bonding includes forming a bond region having an interface between the first bonding layer and the second bonding layer.

2. The method of claim 1, further comprising:

forming a micro-electro-mechanical systems (MEMS) device on at least one of the first substrate and the second substrate.

3. The method of claim 1, further comprising:

forming an integrated circuit on at least one of the first substrate and the second substrate.

4. The method of claim 1, further comprising:

cleaning the first and second substrate prior to the bonding.

5. The method of claim 1, wherein the second substrate includes a multilayer interconnect (MLI), and wherein the MLI includes the second bonding layer.

6. The method of claim 1, wherein the first bonding layer includes amorphous silicon.

7. The method of claim 1, wherein the first bonding layer includes polysilicon.

8. The method of claim 1, further comprising doping the first bonding layer.

9. The method of claim 1, wherein the bonding includes providing a forming gas selected from the group consisting of argon, nitrogen, hydrogen, helium, and combinations thereof.

10. The method of claim 1, wherein the bond between the first bonding layer and the second bonding layer provides an electrical connection between the first substrate and the second substrate.

11. A method, comprising:

forming a first semiconductor device on a first substrate;

forming a first layer on the first substrate, wherein the first layer includes silicon;

forming a second semiconductor device on a second substrate;

forming a second layer on the second substrate, wherein the second layer includes aluminum; and

bonding the first layer and the second layer, wherein the bonding provides an electrical connection between the first substrate and the second substrate.

12. The method of claim 11, wherein the forming the first layer includes doping the first layer.

13. The method of claim 11, wherein the forming the first layer includes a depositing silicon by a deposition process selected from the group consisting of physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, electron beam evaporation (E-Gun), ion beam, energy beam, and combinations thereof.

14. The method of claim 11, wherein at least one of the forming the first semiconductor device and the forming the second semiconductor device includes forming a MEMS device.

15. The method of claim 11, wherein at least one of the forming the first semiconductor device and the forming the second semiconductor device includes using a complementary metal-oxide semiconductor (CMOS) process.

16. The method of claim 11, further comprising:

performing at least one of a wet etch and a dry etch on the first layer and the second layer prior to the bonding.

17. A device, comprising:

a micro-electro-mechanical systems (MEMS) device, disposed on a first substrate;

a semiconductor device, disposed on a second substrate; and

a bond electrically connecting the MEMS device and the semiconductor device, wherein the bond includes an interface between a first bonding layer including silicon and a second bonding layer including aluminum.

18. The device of claim 17, further comprising:

a second bond connecting the MEMS device and the semiconductor device, wherein the second bond includes a second interface between the first bonding layer and the second bonding layer and wherein the second bond provides no electrical connection between the MEMS device and the semiconductor device.

19. The device of claim 17, wherein the semiconductor device is a second MEMS device.

20. The device of claim 17, wherein the semiconductor device is an integrated circuit including at least one complementary metal-oxide semiconductor (CMOS) feature.