Semiconductor Memory Device and Method of Manufacturing the Same

• US 20110233636A1
• Filed: 03/17/2011
• Published: 09/29/2011
• Est. Priority Date: 03/23/2010
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hur, Sung-hoi, Cho, Byung-kyu, Choi, Jung-dal, Seol, Kwang-soo
• Application Number:
  US13/050,320
• Publication Number:
  US 20110233636A1
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures.

Claims

1. A non-volatile memory device comprising:

a substrate;

at least two gate structures on the substrate; and

at least one impurity region that is at least partially disposed in a portion of the substrate between the at least two gate structures;

wherein a center of the at least one impurity region is horizontally offset from a center of a region between the at least two gate structures.

2. The non-volatile memory device of claim 1, wherein the at least two gate structures comprise a first gate structure and a second gate structure;

and

wherein the first gate structure is configured to receive a programming voltage for performing a programming operation with respect to the non-volatile memory device before the programming voltage is applied to the second gate structure.

3. The non-volatile memory device of claim 2, wherein the center of the at least one impurity region is closer to the second gate structure than the first gate structure.

4. The non-volatile memory device of claim 2, wherein the at least one impurity region is at least partially disposed below the second gate structure.

5. The non-volatile memory device of claim 1, wherein the at least two gate structures comprise a plurality of gate structures arranged in a row on the substrate, wherein the at least one impurity region comprises a plurality of impurity regions, and wherein each of the plurality of impurity regions is between two adjacent gate structures of the plurality of gate structures.

6. The non-volatile memory device of claim 5, further comprising:

a first selection transistor on the substrate and adjacent to the first gate structure of the plurality of gate structures, the first selection transistor being connected to a bit line; and

a second selection transistor on the substrate and adjacent to an N^th gate structure of the plurality of gate structures, the second selection transistor being connected to a common source line;

wherein N is in integer equal to or greater than 2.

7. The non-volatile memory device of claim 6, wherein the center of each of the plurality of impurity regions is horizontally offset toward one of two gate structures adjacent to the respective impurity regions that is closer to the second selection transistor.

8. The non-volatile memory device of claim 6, wherein the center of each of the plurality of impurity regions is located horizontally offset toward one of two gate structures adjacent to the respective impurity regions that is closer to the first selection transistor.

9. The non-volatile memory device of claim 1, wherein the at least one impurity region has a shape that is symmetrical with respect to a vertical axis running through the center of the at least one impurity region.

10. The non-volatile memory device of claim 1, wherein the at least one impurity region has a shape that is asymmetrical with respect to a vertical axis running through the center of the at least one impurity region.

11. The non-volatile memory device of claim 1, wherein the at least two gate structures each comprise a tunneling insulation layer on the substrate, a charge storage layer on the tunneling insulation layer, an interlayer insulation layer on the charge storage layer, and a gate electrode layer on the interlayer insulation layer.

12-23. -23. (canceled)

24. A non-volatile memory device comprising:

a semiconductor layer;

a pair of gate structures on the semiconductor layer and defining a region of the semiconductor layer between the pair of gate structures; and

an impurity region in the semiconductor layer, wherein the impurity region is at least partially disposed in the region of the semiconductor layer between the pair of gate structures and comprises a source/drain region for both of the pair of gate structures;

wherein a center of the impurity region is horizontally offset from a center of the region of the semiconductor layer between the pair of gate structures.

25. The non-volatile memory device of claim 24, wherein the impurity region is at least partially disposed beneath a first one of the pair of gate structures.

26. The non-volatile memory device of claim 25, wherein the impurity region does not extend beneath a second one of the pair of gate structures.

27. The non-volatile memory device of claim 24, wherein the semiconductor layer has a first conductivity type;

and

wherein the region of the semiconductor layer between the pair of gate structures comprises a first sub-region doped with second conductivity type impurities and a second sub-region that is free of second conductivity type impurities, wherein the second conductivity type is opposite the first conductivity type.

28. The non-volatile memory device of claim 24, wherein the semiconductor layer has a first conductivity type;

and

wherein the region of the semiconductor layer between the pair of gate structures comprises a first sub-region doped with first and second conductivity type impurities and that has a net conductivity of the second conductivity type and a second sub-region that is doped with both first and second conductivity type impurities and that has a net conductivity of the first conductivity type, wherein the second conductivity type is opposite the first conductivity type.