SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20110233637A1
• Filed: 03/21/2011
• Published: 09/29/2011
• Est. Priority Date: 03/23/2010
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Arai, Norihisa, HATANO, Tomoaki
• Application Number:
  US13/052,156
• Publication Number:
  US 20110233637A1
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor

Abstract

According to one embodiment, a method for manufacturing a semiconductor device comprises forming a first insulating film on a semiconductor substrate, processing the first insulating film into a predetermined pattern, forming a first gate electrode structure on the first insulating film, the first gate electrode structure having a smaller width than that of the processed first insulating film in a channel length direction, introducing a first impurity of a first conductivity type into the semiconductor substrate via the processed first insulting film using the first gate electrode structure as a mask, and introducing a second impurity of the first conductivity type into the semiconductor substrate using the first gate electrode structure and the first insulating film as a mask.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

forming a first insulating film on a semiconductor substrate;

processing the first insulating film into a predetermined pattern;

forming a first gate electrode structure on the first insulating film, the first gate electrode structure having a smaller width than that of the processed first insulating film in a channel length direction;

introducing a first impurity of a first conductivity type into the semiconductor substrate via the processed first insulting film using the first gate electrode structure as a mask; and

introducing a second impurity of the first conductivity type into the semiconductor substrate using the first gate electrode structure and the first insulating film as a mask.

2. The method according to claim 1, wherein the second impurity introduced into the semiconductor substrate has a greater concentration than that of the first impurity introduced into the semiconductor substrate.

3. The method according to claim 1, wherein the first conductivity type is a P type.

4. The method according to claim 1, wherein the first impurity is boron.

5. The method according to claim 1, wherein processing the first insulating film into the predetermined pattern comprises wet-etching the first insulating film.

6. The method according to claim 1, further comprising:

forming a second insulating film with a smaller film thickness than that of the first insulating film on the semiconductor substrate in a region in which the pattern of the first insulating film is not provided, after processing the first insulating film into the predetermined pattern; and

forming a second gate electrode structure on the second insulating film,

wherein introducing the first impurity comprises introducing the first impurity of the first conductivity type into the semiconductor substrate using the second gate electrode structure as a mask.

7. The method according to claim 6, further comprising:

introducing a third impurity of a second impurity type into the semiconductor substrate using the first gate electrode structure and the first insulating film as well as the second gate electrode structure as a mask.

8. The method according to claim 7, wherein the first conductivity type is a P type and the second conductivity type is an N type.

9. The method according to claim 6, wherein the second insulating film and the second gate electrode structure are included in a memory cell transistor.

10. The method according to claim 1, further comprising forming a third insulating film after introducing the second impurity into the semiconductor substrate, the third insulating film having a smaller film thickness than that of the first insulating film and covering the semiconductor substrate in which the second impurity has been introduced, the first gate electrode structure, and a part of the first insulating film which projects from the first gate electrode structure.

11. The method according to claim 10, wherein a third insulating film is a silicon nitride film.

12. The method according to claim 1, wherein the region in the semiconductor substrate in which the second impurity has been introduced is surrounded by a region in the semiconductor substrate in which the first impurity has been introduced.

13. The method according to claim 1, wherein introducing the second impurity comprises introducing the second impurity into the first insulating film.

14. A semiconductor device comprising:

paired first impurity diffusion regions of a P type formed in a surface region of a semiconductor substrate;

paired second impurity diffusion regions of a P type sandwiched between the paired first impurity diffusion regions and formed adjacent to the paired first impurity diffusion regions, the paired second impurity diffusion regions having a lower impurity concentration than that of the first impurity diffusion regions;

a channel region sandwiched between the paired second impurity diffusion regions;

a gate insulating film formed on the second impurity diffusion regions and on the channel region; and

a gate electrode formed on the gate insulating film and substantially immediately above the channel region and having a smaller width than that of the gate insulating film in a channel length direction, wherein the paired first impurity diffusion regions are formed in a self-aligned manner with respect to the gate insulating film.

15. The device according to claim 14, further comprising a peripheral insulating film formed on the first impurity diffusion regions as well as the gate electrode and a part of the gate insulating film which projects from the gate electrode, the gate insulating film having a greater film thickness than that of the peripheral insulating film.

16. The device according to claim 15, wherein the peripheral insulating film is a silicon nitride film.

17. The device according to claim 14, wherein the impurity contained in the second impurity diffusion regions is boron.

18. The device according to claim 14, wherein the first impurity diffusion regions are surrounded by the second impurity diffusion regions.

19. The device according to claim 14, wherein the gate insulating film contains a P-type impurity.

20. The device according to claim 14, further comprising a plurality of memory cell transistors and a low-withstand-voltage transistor formed on the semiconductor substrate,

wherein the gate insulating film has a greater film thickness than that of the memory cell transistors and the low-withstand-voltage transistor.