Three-Dimensional Semiconductor Memory Devices And Methods Of Fabricating The Same

• US 20110233648A1
• Filed: 03/25/2011
• Published: 09/29/2011
• Est. Priority Date: 03/26/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nakanishi, Toshiro, Yoo, Dongchul, Hwang, Wansik, Choi, Hanmei, Park, Chanjin, Seol, Kwang Soo, Hwang, Kihyun, Hur, Sunghoi, Lee, Juyul, Park, Kwangmin
• Granted Patent: US 9,536,970 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Claims

1. A three-dimensional semiconductor device, comprising:

an electrode structure including a stacked plurality of electrodes on a substrate;

a plurality of semiconductor patterns penetrating the electrode structure; and

a plurality of memory elements between the semiconductor patterns and the electrode structure, the memory elements including a first pattern extending in a first direction to cross the plurality of electrodes and a second pattern extending in a second direction orthogonal to the first direction to cross the plurality of semiconductor patterns.

2. The device of claim 1, wherein the second pattern is substantially conformal to top and bottom surfaces of the electrodes, and to sidewalls of the electrodes adjacent to the semiconductor patterns.

3. The device of claim 1, further comprising:

a plurality of interlayer insulating layers between the electrodes in the first direction,

wherein the first pattern extends between sidewalls of the semiconductor patterns and sidewalls of the electrodes, and between the sidewalls of the semiconductor patterns and sidewalls of the interlayer insulating layers, and

the second pattern extends between the sidewalls of the semiconductor patterns and the sidewalls of the electrodes, and between surfaces of the interlayer insulating layers.

4. The device of claim 3, further comprising:

a capping layer between the semiconductor patterns and the interlayer insulating layers, the capping layer being of a different material than the interlayer insulating layers.

5. The device of claim 4, wherein the capping layer extends in the first direction between the electrodes and the semiconductor patterns, and between the interlayer insulating layers and the semiconductor patterns, and

the capping layer is thinner between the electrodes and the semiconductor patterns than between the interlayer insulating layers and the semiconductor pattern.

6. The device of claim 4, wherein the second pattern is in direct contact with a sidewall of the first pattern, and

the capping layer includes regions separated in the first direction by the second pattern.

7. The device of claim 1, wherein at least one of a chemical composition and an electrical property of the first and second patterns is substantially identical.

8. The device of claim 1, wherein two different types of atoms with greatest atomic percent concentrations in a chemical composition of the second pattern are identical to two types of atoms with greatest atomic percent concentrations in a chemical composition of the first pattern.

9. The device of claim 1, wherein the memory elements include a charge storing layer, a tunnel insulating layer, and a blocking insulating layer,

the tunnel insulating layer is between the charge storing layer and the semiconductor pattern,

the tunnel insulating layer includes at least one insulating layer,

the blocking insulating layer includes at least one insulating layer, and

the blocking insulating layer is between the charge storing layer and the electrodes.

10. The device of claim 9, wherein

the first pattern includes the tunnel insulating layer, and

the second pattern includes the charge storing layer and the blocking insulating layer.

11. The device of claim 9, wherein

the first pattern includes the tunnel insulating layer and the charge storing layer, and

the second pattern includes the blocking insulating layer.

12. The device of claim 11, wherein the second pattern is a different material than the charge storing layer, and

the first pattern includes a capping layer between the charge storing layer and the blocking insulating layer.

13. The device of claim 9, wherein both the second pattern and the first pattern include one of the tunnel insulating layer, the blocking insulating layer, and the charge storing layer.

14. The device of claim 13, wherein the second pattern and the first pattern contact each other between the sidewalls of the electrodes and the semiconductor pattern, and

two different types of atoms with greatest atomic percent concentrations in a chemical composition of the second pattern are identical to two types of atoms with greatest atomic percent concentrations in a chemical composition of the first pattern contacting the second pattern.

15. The device of claim 9, wherein

at least one insulating layer of the tunnel insulating layer and at least one insulating layer of the blocking insulating layer include materials with a higher band gap than the charge storing layer, and

a dielectric constant of a material of at least one insulating layer of the blocking insulating layer is larger than a dielectric constant of a material of at least one insulating layer of the tunnel insulating layer.

16. The device of claim 9, wherein

the tunnel insulating layer includes at least one silicon oxide layer,

the charge storing layer includes one of an insulating layer with a higher density of trap sites than a silicon oxide layer and an insulating layer with intrinsic conductive nano particles, and

the blocking insulating layer includes at least one of an aluminum oxide layer, a hafnium oxide layer, a zirconium oxide layer, a tantalum oxide layer, a titanium oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

17. The device of claim 1, wherein the electrodes include at least one of doped silicon, a metal, a metal nitride, and a metal silicide.

18. The device of claim 1, wherein the electrodes include a conductive material with lower resistivity than doped silicon.

19. The device of claim 1, wherein the semiconductor patterns include

a semiconductor spacer in the first pattern, and

a semiconductor body in the spacer, and

an end of the body extends farther than an end of the spacer.

20. The device of claim 19, wherein the body directly contacts the substrate, and

the spacer is separated from the substrate.

21. The device of claim 19, wherein the body includes

a core region covering an inner wall of the semiconductor spacer, and

a connection region extending from the core region and through a plane of a surface of the substrate.

22. The device of claim 21, wherein the connection region of the body further extends in the second direction and is wider than the spacer.

23. The device of claim 21, wherein the connection region of the body extends below the memory element to directly contact an inner sidewall of a recess in the substrate, and

the body covers an end surface of the first pattern.

24. The device of claim 19, wherein the substrate is a semiconductor material with fewer crystal defects than the body.

25. The device of claim 19, wherein an end of the spacer extends farther than an end of the first pattern.

26. The device of claim 1, further comprising:

a selection structure between the electrode structure and the substrate,

wherein the selection structure includes selection lines and a selection active pattern penetrating the selection lines to connect the semiconductor pattern with the substrate, and

ends of the first pattern do not intersect the selection lines.

27. The device of claim 1, wherein

the first pattern includes a charge storing layer, a tunnel insulating layer between the charge storing layer and the semiconductor pattern, and a capping layer between the charge storing layer and the electrode,

the charge storing layer extends farther towards a surface of the substrate than the capping layer and the tunnel insulating layer, and

an end of the capping layer is closer to a surface of the substrate than an end of the tunnel insulating layer.

28. The device of claim 1, wherein the substrate includes

a contact region contacting the semiconductor pattern, and

a source region spaced apart from the contact region,

the contact region is a same conductive type as the semiconductor pattern, and

the source region is a different conductive type than the contact region.

29. The device of claim 28, further comprising:

a source conductive pattern penetrating the electrode structure to contact the source region.

30. A method of fabricating a three-dimensional semiconductor device, the method comprising:

forming a mold structure including a plurality of mold layers alternately stacked with a plurality of sacrificial layers on a substrate;

forming an opening penetrating the mold structure;

sequentially forming a first pattern and a semiconductor pattern on an inner wall of the mold structure inside the opening;

forming recess regions between the mold layers by removing the sacrificial layers; and

sequentially forming a second pattern and an electrode between the mold layers in the recess region.

31. The method of claim 30, wherein

the forming of the first pattern includes forming a tunnel insulating layer,

the forming of the second pattern includes sequentially forming a charge storing layer and a blocking insulating layer,

the tunnel insulating layer and the blocking insulating layer are each formed to include a material with a larger band gap than a material included in the charge storing layer, and

the blocking insulating layer is formed to include a material with a larger dielectric constant than a material included in the tunnel insulating layer.

32. The method of claim 30, wherein

the forming of the first pattern includes sequentially forming a charge storing layer and a tunnel insulating layer,

the forming of the second pattern includes forming a blocking insulating layer,

the tunnel insulating layer and the blocking insulating layer are each formed to include a material with a larger band gap than a material included in the charge storing layer, and

the blocking insulating layer is formed of a material with a larger dielectric constant than a material included in the tunnel insulating layer.

33. The method of claim 32, wherein

the tunnel insulating layer is formed after the forming of the charge storing layer, and

the blocking insulating layer is formed after the forming of the charge storing layer.

34. The method of claim 32, wherein the forming of the first pattern includes forming a capping layer before the forming of the charge storing layer, the capping layer being formed of a different material than the charge storing layer.

35. The method of claim 34, wherein the forming of the recess regions includes isotropically etching the sacrificial layer by using an etchant with etch selectivity, the sacrificial layer being selectively etched with respect to the mold layer and the capping layer.

36. The method of claim 34, further comprising:

exposing an outer wall of the charge storing layer by etching the capping layer exposed by the recess region before the forming of the second pattern.

37. The method of claim 30, wherein the forming of the first and second patterns includes forming the second pattern with a material of substantially a same chemical composition as the first pattern, such that two different types of atoms with greatest atomic percent concentrations in the chemical composition of the second pattern are identical to two types of atoms with greatest atomic percent concentrations in the chemical composition of the first pattern.

38. The method of claim 30, wherein the forming of the first pattern and the semiconductor pattern includes

sequentially forming a first layer and a first semiconductor layer on an inner wall of the mold structure in the opening,

forming a first semiconductor pattern exposing the first layer at a bottom of the opening by isotropically etching the first semiconductor layer, and

isotropically etching the first layer by using the first semiconductor pattern as an etch mask.

39. The method of claim 38, wherein the forming of the first pattern and the semiconductor pattern further includes

anisotropically etching through the first layer in the opening using the first semiconductor pattern as an etch mask before the isotropic etching of the first layer.

40. The method of claim 30, further comprising:

forming a selection active pattern,

wherein the forming of the mold layer includes forming the mold layer on the selection active pattern, and

the forming of the semiconductor pattern includes forming the semiconductor pattern to connect to the substrate via the selection active pattern.

41. A three-dimensional semiconductor device, comprising:

an electrode structure including a plurality of electrodes stacked sequentially on a substrate;

a plurality of interlayer insulating layers between the plurality of electrodes, respectively;

a semiconductor pattern penetrating the electrode structure;

a first pattern between the electrodes and the semiconductor pattern and between the electrodes and the interlayer insulating layers; and

a second pattern between the semiconductor pattern and the interlayer insulating layer, at least one of a chemical composition and an electrical property of the first pattern substantially identical to a corresponding one of a chemical composition and an electrical property of the second pattern.

42. The device of claim 41, wherein the second pattern extends between sidewalls of the first pattern and the semiconductor pattern.

43. The device of claim 41, wherein two kinds of atoms with greatest atomic percent concentrations in the chemical composition of the first pattern are identical to two types of atoms with greatest atomic percent concentrations in the chemical composition of the second pattern.

44. A three-dimensional semiconductor device, comprising:

a selection structure on a semiconductor substrate, the selection structure including a plurality of selection lines, a selection active pattern, and a selection gate insulating layer, the selection active pattern penetrating the selection lines to contact the semiconductor substrate, the selection gate insulating layer between the selection lines and the selection active pattern; and

a memory structure stacked on the selection structure, the memory structure including a plurality of word lines, a memory active pattern, and a memory gate insulating layer, the memory active pattern penetrating the word lines to contact the selection active pattern, the memory gate insulating layer between the word lines and the memory active pattern, at least a portion of the memory gate insulating layer covering at least a portion of opposing surfaces of each of the word lines.

45. The device of claim 44, wherein

an end of the selection active pattern extends through a plane of a surface of the semiconductor substrate, and

the selection gate insulating layer is localized between the selection active pattern and sidewalls of the selection lines so that the end of the selection active pattern directly contacts the semiconductor substrate.

46. The device of claim 44, wherein

the semiconductor substrate is recessed,

the selection active pattern extends into the recess, and

a width of the recess is about identical to a width of the selection active pattern in the recess.

47. The device of claim 44, wherein

the selection active pattern is one of a semiconductor of a same conductive type as a surface of the semiconductor substrate in contact with the selection active pattern and an intrinsic semiconductor, and

the selection active pattern is one of a semiconductor of a same conductive type as the memory active pattern and an intrinsic semiconductor.

48. The device of claim 44, wherein the selection active pattern includes

a sidewall penetrating the selection lines, and

an end extending from the sidewall to cover a top surface of the semiconductor substrate, and

a thickness of the sidewall in a direction parallel to a plane of the substrate is substantially a same thickness as a thickness of the end in a direction orthogonal to the plane of the substrate, such that at least a part of the selection active pattern is U-shaped.

49. The device of claim 44, wherein the selection active pattern includes one of a rectangular and trapezoidal section that does not overlap the memory active pattern.

50. The device of claim 44, wherein the memory gate insulating layer includes

a blocking insulating layer adjacent to the word line,

a tunnel insulating layer adjacent to the memory active pattern, and

a charge storing layer between the blocking insulating layer and the tunnel insulating layer, and

at least one of a material and thickness of the selection gate insulating layer is different from the memory gate insulating layer.

51. The device of claim 50, wherein at least one of a material and thickness of the selection gate insulating layer is substantially identical to the blocking insulating layer.

52. The device of claim 50, wherein

the tunnel insulating layer crosses over a plurality of word lines stacked in a direction orthogonal to a plane of the substrate, and

the blocking insulating layer crosses over a plurality of memory active patterns arranged in a direction parallel to the plane of the substrate.

53. The device of claim 44, wherein

the selection active pattern is silicon,

the selection gate insulating layer is a silicon oxide layer localized to a region between the selection active pattern and the selection lines, and

the selection active pattern is thinner in the region than elsewhere.

54. A method of fabricating a three-dimensional structure device, the method comprising:

forming a mold structure on a substrate;

forming an opening penetrating through the mold structure and a surface of the substrate so that a recess is formed in the substrate;

sequentially forming a first layer and a first semiconductor layer to cover an inner wall of the mold structure in the opening and the substrate in the recess;

forming a penetrating dent to penetrate through the first semiconductor layer and the first layer to expose a surface of the substrate in the recess;

forming an under-cut region exposing a sidewall of the substrate in the recess by isotropically etching the first layer exposed by the penetrating dent; and

forming a second semiconductor layer in the under-cut region to connect the substrate and the first semiconductor layer.

55. The method of claim 54, wherein

the first layer and the first semiconductor layer are sequentially formed to substantially and conformally cover the inner wall in the opening,

a sum of deposition thicknesses of the first layer and the first semiconductor layer is less than the half a width of the opening, and

the forming of the penetrating dent includes

anisotropically etching the first semiconductor layer in the opening to form a semiconductor spacer, a surface of the first layer being exposed by the anisotropic etch, and

anisotropically etching the exposed first layer.

56. The method of claim 55, wherein

the forming of the penetrating dent further includes forming a protective layer spacer on an inner sidewall of the first semiconductor layer before the anisotropic etch of the first semiconductor layer, and

the protective layer spacer is formed of a material with etch selectivity to the first semiconductor layer and is formed thinner than half of a difference between the half of the width of the opening and the sum of deposition thicknesses.

57. The method of claim 56, wherein

the forming of the penetrating dent further includes isotropically etching the first semiconductor layer by using the protective layer spacer as an etch mask before the forming of the under-cut region.

58. The method of claim 56, wherein the protective layer spacer is removed during the forming of the under-cut region.

59. The method of claim 54, wherein the forming of the first layer includes forming the first layer to include a capping layer, a charge storing layer, and a tunnel layer, and

the forming of the under-cut region includes

forming a first under-cut region by isotropically etching the charge storing layer exposed by the penetrating dent, and

forming a second under-cut region by isotropically etching the capping layer and the tunnel layer exposed by the penetrating dent and the first under-cut region.

60. The method of claim 54, wherein the forming of the first layer includes forming the first layer to include a capping layer, a charge storing layer, and a tunnel layer, which sequentially cover an inner wall of the opening, and

the forming of the under-cut region includes

forming a first under-cut region by isotropically etching the tunnel layer and the capping layer exposed by the penetrating dent, and

forming a second under-cut region by isotropically etching the charge storing layer exposed by the penetrating dent and the first under-cut region.

61. A method of fabricating a three-dimensional structure device, the method comprising:

forming a multi-layered structure on a substrate;

forming an opening penetrating the multi-layered structure and recessing a surface of the substrate;

sequentially forming a first layer and a first semiconductor layer to cover an inner wall of the multi-layered structure and the recessed substrate in the opening;

forming a protective layer spacer on an inner sidewall of the first semiconductor layer;

forming an under-cut region to expose a sidewall of the recessed substrate in the opening by sequentially and isotropically etching the first semiconductor layer and the first layer using the protective layer spacer as an etch mask; and

forming a second semiconductor layer in the under-cut region to connect the substrate with the first semiconductor layer.

62. The method of claim 61, wherein the isotropic etch of the first semiconductor layer includes exposing a surface of the first layer by dry-etching an exposed surface of the first semiconductor layer in an atmosphere not including an intentionally-generated plasma.

63. The method of claim 62, wherein the dry-etch of the exposed surface of the first semiconductor layer includes using at least one of a first gas including fluorine atoms, a second gas including chlorine atoms, and a carrier gas including at least one of argon, helium and nitrogen.

64. The method of claim 62, wherein the dry-etch of the exposed surface of the first semiconductor layer includes dry-etching under a pressure of less than about 1 atmosphere and a temperature of about 350°

C. to about 500°

C.

65. The method of claim 61, wherein the isotropic etch of the first layer includes etching a surface of the first layer using an etchant, the surface of the first layer being exposed by the isotropic etch of the first semiconductor layer.

66. The method of claim 65, wherein the etchant includes a liquid that selectively etches a material of the first layer with respect to a material of the first semiconductor layer.

67. The method of claim 61, wherein the first layer includes a plurality of layers, and

at least one of the layers is one of a silicon oxide layer and a silicon nitride layer.

68. The method of claim 61, wherein

the first layer includes a capping layer, a charge storing layer, and a tunnel insulating layer,

the isotropic etch of the first layer includes sequentially etching the tunnel insulating layer, the charge storing layer, and the capping layer,

the etching of the tunnel insulating layer and the capping layer includes etching the tunnel insulating layer and the capping layer with an etchant including fluorine acid, and

the etching of the charge storing layer includes etching the charge storing layer with an etchant including phosphoric acid.

69. The method of claim 61, wherein the protective layer spacer is removed during the isotropic etch of the first layer.