SEMICONDUCTOR POWER DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110233659A1
• Filed: 07/01/2010
• Published: 09/29/2011
• Est. Priority Date: 03/29/2010
• Status: Active Grant

• Current Assignee: Sinopower Semiconductor, Inc.
• Original Assignee: Sinopower Semiconductor, Inc.
• Inventors: TAI, SUNG-SHAN
• Granted Patent: US 8,334,566 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor power device is provided, and a manufacturing method thereof includes the following steps. First, a substrate is provided, and an epitaxial layer is formed on the substrate. Then, at least a first trench and at least a second trench are formed in the epitaxial layer. Subsequently, a shield electrode and a termination electrode are respectively formed in the first trench and the second trench, and upper sidewalls of the first trench and the second trench are exposed. Following that, a gate dielectric layer is covered. Then, a second conductive layer is deposited to fill up the first trench and partially fill in the second trench. Subsequently, the second conductive layer is etched to remove the second conductive layer in the second trench and form a gate electrode in the first trench. Accordingly, the present invention can reduce the number of masks.

Claims

1. A manufacturing method of a semiconductor power device, comprising:

providing a substrate;

forming an epitaxial layer on the substrate;

forming at least a first trench and at least a second trench in the epitaxial layer;

depositing a first conductive layer to fill the first trench and the second trench;

etching the first conductive layer to form a shield electrode in the first trench, to form a termination electrode in the second trench, and to expose an upper sidewall of the first trench and an upper sidewall of the second trench;

forming a gate dielectric layer to cover the upper sidewall of the first trench, the upper sidewall of the second trench, the shield electrode, and the termination electrode;

depositing a second conductive layer on the gate dielectric layer to fill up the first trench and partially fill in the second trench; and

etching the second conductive layer to remove the second conductive layer in the second trench and to form a gate electrode in the first trench.

2. The manufacturing method of claim 1, wherein a width of the second trench is greater than a width of the first trench.

3. The manufacturing method of claim 1, wherein the second trench extends into the substrate.

4. The manufacturing method of claim 1, wherein before the first conductive layer is formed, the manufacturing method further comprises forming a first dielectric layer on a surface of the first trench and on a surface of the second trench.

5. The manufacturing method of claim 4, wherein before the first dielectric layer is formed, the manufacturing method further comprises forming a doped region under the second trench.

6. The manufacturing method of claim 1, wherein the second conductive layer is etched by an isotropic etching process.

7. The manufacturing method of claim 1, wherein the second conductive layer is a polysilicon layer, and the manufacturing method further comprises performing an oxidation process after etching the second conductive layer.

8. The manufacturing method of claim 1, further comprising forming a body region in the epitaxial layer and around the first trench, and forming a source region in the body region and around the first trench.

9. The manufacturing method of claim 8, further comprising forming an inter-layer dielectric layer to cover the source region, the gate electrode, and the gate dielectric layer.

10. The manufacturing method of claim 9, further comprising forming a plurality of contact holes in the inter-layer dielectric layer and in the gate dielectric layer to respectively expose the source region, the termination electrode, and the gate electrode.

11. The manufacturing method of claim 10, further comprising depositing a source metal layer on the inter-layer dielectric layer, wherein the source metal layer is filled in the contact hole of exposing the source region and in the contact hole of exposing the termination electrode, and the source metal layer is electrically connected to the source region and the termination electrode.

12. The manufacturing method of claim 10, further comprising depositing a gate metal layer on the inter-layer dielectric layer, wherein the gate metal layer is filled in the contact hole of exposing the gate electrode, and the gate metal layer is electrically connected to the gate electrode.

13. A semiconductor power device, comprising:

a substrate;

an epitaxial layer, disposed on the substrate, wherein the epitaxial layer comprises at least a first trench and a second trench;

a gate structure disposed in the first trench, the gate structure comprising;

a shield electrode and a gate electrode, the shield electrode being disposed under the gate electrode; and

a gate dielectric layer, disposed on an upper sidewall of the first trench and between the gate electrode and the epitaxial layer;

a termination structure disposed in the second trench, the termination structure comprising;

a termination electrode, wherein the termination electrode and the shield electrode are connected to each other; and

a dielectric layer disposed between the termination electrode and a sidewall of the second trench; and

a body region disposed in the epitaxial layer, wherein the second trench is only surrounded by the body region.

14. The semiconductor power device of claim 13, wherein the second trench extends into the substrate.

15. The semiconductor power device of claim 13, further comprising a doped region disposed under the second trench.

16. The semiconductor power device of claim 15, wherein a conductive type of the doped region and a conductive type of the epitaxial layer are the same.

17. The semiconductor power device of claim 13, wherein the epitaxial layer comprises the body region and a source region around the first trench, and the semiconductor power device further comprises an inter-layer dielectric layer to cover the source region, the gate electrode, and the gate dielectric layer.

18. The semiconductor power device of claim 17, wherein the inter-layer dielectric layer and the gate dielectric layer comprise a plurality of contact holes to respectively expose the source region, the termination electrode, and the gate electrode.

19. The semiconductor power device of claim 18, further comprising a source metal layer disposed on the inter-layer dielectric layer, wherein the source metal layer is electrically connected to the source region through the contact hole of exposing the source region, and the source metal layer is electrically connected to the termination electrode through the contact hole of exposing the termination electrode.

20. The semiconductor power device of claim 18, further comprising a gate metal layer disposed on the inter-layer dielectric layer, wherein the gate metal layer is electrically connected to the gate electrode through the contact hole of exposing the gate electrode.