Semiconductor device and a method of manufacturing the same

• US 20110233664A1
• Filed: 06/09/2011
• Published: 09/29/2011
• Est. Priority Date: 08/04/2003
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shiraishi, Masaki, Nakazawa, Yoshito
• Application Number:
  US13/067,566
• Publication Number:
  US 20110233664A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p⁻ type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p⁻type semiconductor region is formed under a n⁺type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

Claims

1. A semiconductor device including a trench gate type MISFET,

the trench gate type MISFET comprising:

a semiconductor substrate of a first conductivity type;

a first semiconductor layer of the first conductivity type formed on the semiconductor substrate and serving as a drain region of the MISFET;

a first, a second and a third trench formed on the top surface of the first semiconductor layer (FIGS. 9-11),

the first trench arranged, in a first direction, adjacent to the second trench such that a distance, in the first direction, of a first region of the top surface is defined by the first trench and the second trench (FIG. 26),

the second trench arranged, in the first direction, adjacent to the third trench such that a distance, in the first direction, of the second region of the top surface is defined by the second trench and the third trench (FIG. 26);

a gate insulating film of the MISFET formed on an inner surface of the trenches;

a gate electrode of the MISFET formed on the gate insulating film in the trench;

a second semiconductor region (13) of a second conductivity type opposite to the first conductivity type formed at the first region and on the first semiconductor layer,

the second semiconductor region (13) being in contact with the first and the second trench and serving as a channel forming region of the MISFET;

a third semiconductor region (13) of the second conductivity type opposite to the first conductivity type formed at the second region and on the first semiconductor layer,

the third semiconductor region (13) being in contact with the second and the third trench such that the third semiconductor region (13) is formed to be in contact with a bottom surfaces of the second and the third trench; and

a fourth semiconductor region of the first conductivity type formed at the first region and on the second semiconductor layer and serving as a source region of the MISFET.

2. The device according to claim 1, wherein the first trench is integrally formed with the second trench (FIGS. 10-11).

3. The device according to claim 1, wherein the third semiconductor region (13) is formed to extend under the second trench and the third trench (FIG. 26).