DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH AND THREE OR FOUR MASKS PROCESS

• US 20110233667A1
• Filed: 05/18/2010
• Published: 09/29/2011
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Xiaobin, Tai, Sung-Shan, Lui, Sik
• Granted Patent: US 8,394,702 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Claims

1. A method for making a semiconductor device, comprising:

a) providing a semiconductor substrate;

b) applying a first mask on top of the semiconductor substrate;

and forming trenches TR1, TR2 with widths W1, W2, respectively, wherein W1 is narrower than W2, wherein the trenches TR2 include first and second gate runner trenches connected to the trenches TR1, wherein at least one of the first and second gate runner trenches abuts and surrounds the trenches TR1;

c) forming a gate insulator on the bottoms and sidewalls of the trenches TR1, TR2, with corresponding thickness T1, T2 wherein T2 is greater than T1;

d) forming a conductive material in the trenches TR1 to form gate electrodes and forming a conductive material in the trenches TR2, to form first and second gate runners and a termination structure, wherein the first and second gate runners are in electrical contact with the gate electrodes;

e) forming a body layer in a top portion of the semiconductor substrate;

f) forming a source layer in a top portion of the body layer;

g) applying an insulator layer on top of the semiconductor substrate;

h) applying a second mask on top of the insulator layer;

i) forming electrical contacts through contact openings in the insulator layer using the second mask, wherein the contact openings include source openings to the source layer proximate each gate electrode, gate runner contact openings to the gate runners, termination contact openings to the termination structure, and a short contact opening to the source layer or body layer proximate the die edge; and

j) forming first and second metal regions on the insulator layer that are electrically isolated from each other, wherein the first metal region is in electrical contact with the gate runners and wherein the second metal region is in electrical contact with the source contacts,

wherein the thickness T2 is thick enough to support the blocking voltage.

2. The method of claim 1 wherein:

b) further comprises forming trench T3 with width W3, wherein W1 is narrower than W3 and wherein the trench TR3 includes a termination trench that surrounds the trenches TR1 and the gate runner trenches TR2;

c) further comprises forming gate insulator on the bottoms and sidewalls of the trenches TR3 with corresponding thickness T3, wherein T3 is greater than T1;

d) further comprises forming a conductive material in the TR3, to form a termination structure, wherein the termination structure is electrically isolated from the gate runners and the gate electrodes;

i) further comprises forming electrical contacts through contact openings in the insulator layer using the second mask, wherein the contact openings include termination contact openings to the termination structure, and a short contact opening to the source layer or body layer proximate the die edge; and

j) further comprises forming a third metal region on the insulator layer, wherein the third metal region is in electrical contact with the termination contact and the short contact, whereby the termination structure is shorted to the body region at the die edge,

wherein the thickness T3 is thick enough to support the blocking voltage.

3. The method of claim 1 wherein e) comprises:

forming a body layer in a top portion of the entire semiconductor substrate.

4. The method of claim 1 wherein j) comprises:

depositing a metal layer on top of the insulator layer;

applying a metal mask on top of the metal layer; and

etching the metal layer to separate the first and second metal regions.

5. The method of claim 1 wherein c) comprises:

applying a mask to form gate insulator layers on the bottom and sidewalls of trenches TR1, TR2 with corresponding thicknesses T1, T2 wherein T2 is greater than T1.

6. The method of claim 1, wherein c) comprises:

forming a first gate insulator layer at bottom and sidewall of the trenches TR1, TR2;

applying a gate insulator mask on top of the thin insulator layer, wherein the gate insulator mask covers the trenches TR2 but not trenches TR1;

removing the first gate insulator from portions of the semiconductor substrate not covered by the second mask including the trenches TR1; and

forming second gate insulator in the trenches TR1, wherein the second gate insulator is thinner than the first gate insulator.

7. The method of claim 6 wherein e) is performed by implanting ions at sufficiently high energy that the ions can be implanted into the semiconductor substrate through the second gate insulator and the first gate insulator.

8. The method of claim 7, wherein f) is performed by implanting ions at an energy for which the ions can be implanted into the semiconductor substrate through the second gate insulator but not the first gate insulator.

9. The method of claim 8 wherein the source layer is only formed in the top portion of the body layer proximate the trenches TR1.

10. The method of claim 1 wherein c) comprises:

forming a first gate insulator at bottom and sidewall of the trenches TR1, TR2;

forming a sacrificial material that completely fills the trenches TR1 but only lines trenches TR2;

etching back the sacrificial material such that the sacrificial material is removed from trenches TR2 but remains in the trenches TR1;

forming a gate insulator layer in trenches TR2; and

removing the sacrificial material in the trenches TR1, and forming a gate insulator in the trenches TR1,

wherein the gate insulator layer in trenches TR2 have a thickness T2 greater than a thickness T1 of the gate insulator layer in trench TR1.

11. The method of claim 10 wherein the source layer is formed in the top portion of the entire body layer.

12. The method of claim 6 wherein a)-j) are accomplished using no more than four masks.

13. The method of claim 10 wherein a)-j) are accomplished using no more than three masks.

14. The method of claim 1 wherein:

b) further comprises forming trench T3 with width W3, wherein W3 is wider than W2 and wherein the trench TR3 includes a termination trench that surrounds the trenches TR1 and the gate runner trenches TR2;

wherein the method further comprises;

filling the trench TR3 with a dielectric,

wherein the width W3 is thick enough to support the blocking voltage.

15. The method of claim 14 wherein the steps a)-j) only requires three masks.

16. The method of claim 1, wherein b) further comprises forming highly doped channel stop regions under the trenches TR2.

17. A semiconductor device comprising:

a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate;

a first gate runner formed in the semiconductor substrate and electrically connected to the gate electrodes, wherein the first gate runner abuts and surrounds the active region;

a second gate runner connected to the first gate runner for making contact to a gate metal; and

wherein the insulator layer in the gate runner trenches have respective thicknesses T2 greater than a thickness T1 of the gate insulator layer in the active trenches,

wherein the thicknesses T2 is thick enough to support a blocking voltage.

18. The device of claim 17 further comprising:

a termination structure that surrounds the first and second gate runners and the active region, wherein the termination structure includes a conductive material in an insulator-lined trench in the semiconductor substrate, wherein the termination structure is electrically shorted to a source or body layer of the semiconductor substrate near the die edge thereby forming a channel stop for the device.

19. The device of claim 17 further comprising:

a dielectric filled trench that surrounds the first and second gate runners and the active region.

20. The device of claim 19 further comprising a highly doped channel stop region under the dielectric filled trench.

21. The device of claim 17 wherein the semiconductor substrate includes a body layer in the active region and the termination region.

22. The device of claim 21 wherein the semiconductor substrate includes a source region.

23. The device of claim 22 wherein the source region is located only in the active region.

24. The device of claim 17 wherein the first gate runner includes a channel stop region formed under the trench.

25. The device of claim 17 wherein the semiconductor device further comprises a semiconductor substrate having a heavily doped bottom layer and a less heavily doped top layer, wherein the first gate runner trench is deep enough to reach the heavily doped bottom layer.

26. The device of claim 18 wherein the insulator in said insulator-lined trench of the termination structure is thick enough to support the blocking voltage.