DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH AND THREE OR FOUR MASKS PROCESS
First Claim
1. A method for making a semiconductor device, comprising:
- a) providing a semiconductor substrate;
b) applying a first mask on top of the semiconductor substrate;
and forming trenches TR1, TR2 with widths W1, W2, respectively, wherein W1 is narrower than W2, wherein the trenches TR2 include first and second gate runner trenches connected to the trenches TR1, wherein at least one of the first and second gate runner trenches abuts and surrounds the trenches TR1;
c) forming a gate insulator on the bottoms and sidewalls of the trenches TR1, TR2, with corresponding thickness T1, T2 wherein T2 is greater than T1;
d) forming a conductive material in the trenches TR1 to form gate electrodes and forming a conductive material in the trenches TR2, to form first and second gate runners and a termination structure, wherein the first and second gate runners are in electrical contact with the gate electrodes;
e) forming a body layer in a top portion of the semiconductor substrate;
f) forming a source layer in a top portion of the body layer;
g) applying an insulator layer on top of the semiconductor substrate;
h) applying a second mask on top of the insulator layer;
i) forming electrical contacts through contact openings in the insulator layer using the second mask, wherein the contact openings include source openings to the source layer proximate each gate electrode, gate runner contact openings to the gate runners, termination contact openings to the termination structure, and a short contact opening to the source layer or body layer proximate the die edge; and
j) forming first and second metal regions on the insulator layer that are electrically isolated from each other, wherein the first metal region is in electrical contact with the gate runners and wherein the second metal region is in electrical contact with the source contacts,wherein the thickness T2 is thick enough to support the blocking voltage.
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Accused Products
Abstract
A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
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Citations
26 Claims
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1. A method for making a semiconductor device, comprising:
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a) providing a semiconductor substrate; b) applying a first mask on top of the semiconductor substrate; and forming trenches TR1, TR2 with widths W1, W2, respectively, wherein W1 is narrower than W2, wherein the trenches TR2 include first and second gate runner trenches connected to the trenches TR1, wherein at least one of the first and second gate runner trenches abuts and surrounds the trenches TR1; c) forming a gate insulator on the bottoms and sidewalls of the trenches TR1, TR2, with corresponding thickness T1, T2 wherein T2 is greater than T1; d) forming a conductive material in the trenches TR1 to form gate electrodes and forming a conductive material in the trenches TR2, to form first and second gate runners and a termination structure, wherein the first and second gate runners are in electrical contact with the gate electrodes; e) forming a body layer in a top portion of the semiconductor substrate; f) forming a source layer in a top portion of the body layer; g) applying an insulator layer on top of the semiconductor substrate; h) applying a second mask on top of the insulator layer; i) forming electrical contacts through contact openings in the insulator layer using the second mask, wherein the contact openings include source openings to the source layer proximate each gate electrode, gate runner contact openings to the gate runners, termination contact openings to the termination structure, and a short contact opening to the source layer or body layer proximate the die edge; and j) forming first and second metal regions on the insulator layer that are electrically isolated from each other, wherein the first metal region is in electrical contact with the gate runners and wherein the second metal region is in electrical contact with the source contacts, wherein the thickness T2 is thick enough to support the blocking voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor device comprising:
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a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate; a first gate runner formed in the semiconductor substrate and electrically connected to the gate electrodes, wherein the first gate runner abuts and surrounds the active region; a second gate runner connected to the first gate runner for making contact to a gate metal; and wherein the insulator layer in the gate runner trenches have respective thicknesses T2 greater than a thickness T1 of the gate insulator layer in the active trenches, wherein the thicknesses T2 is thick enough to support a blocking voltage. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification