SEMICONDUCTOR CHIP ARRANGEMENT WITH SENSOR CHIP AND MANUFACTURING METHOD

• US 20110233690A1
• Filed: 06/16/2009
• Published: 09/29/2011
• Est. Priority Date: 06/17/2008
• Status: Active Grant

• Current Assignee: TDK Corporation
• Original Assignee: Epcos AG (TDK Corporation)
• Inventors: Feiertag, Gregor, Stelzl, Alois, Krueger, Hans, Leidl, Anton
• Granted Patent: US 8,580,613 B2
• Time in Patent Office: Days
• US Class Current: 257/414
• CPC Class Codes: G01L 19/141 Monolithic housings, e.g. molded or one-piece housings
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

On a carrier (1) an adhesion layer (4), an ASIC chip (2) and a sensor chip (3) are arranged one above another. An interchip connection (5) is provided for electrically connecting the chips among one another, and an ASIC connection (6) is provided for externally electrically connecting the circuit integrated in the ASIC chip.

Claims

1. A semiconductor chip arrangement comprising

a sensor chip having a sensor, and

an ASIC chip having an integrated circuit, wherein

the ASIC chip is arranged on a carrier,

the sensor chip is arranged above a top side of the ASIC chip, said top side facing away from the carrier,

an interchip connection is present which brings about an electrical connection of the sensor to the circuit integrated in the ASIC chip, and

an ASIC connection is present for externally electrically connecting the circuit integrated in the ASIC chip.

2. The semiconductor chip arrangement as claimed in claim 1, wherein

the ASIC chip is fixed on the carrier by means of an adhesion layer.

4. The semiconductor chip arrangement as claimed in claim 2, wherein

the adhesion layer is an adhesive film.

5. The semiconductor chip arrangement as claimed in claim 1, wherein

the ASIC chip is arranged in a cutout in the carrier.

6. The semiconductor chip arrangement as claimed in claim 5, wherein

an insulating layer is present, which bridges an interspace between the ASIC chip and the carrier.

7. The semiconductor chip arrangement as claimed in claim 1, wherein

at least one further sensor chip is arranged above the top side of the ASIC chip, said top side facing away from the carrier.

8. The semiconductor chip arrangement as claimed in claim 1, wherein

by means of a covering layer and/or a filling or by means of a filling with a covering layer applied thereon, a closed housing is formed above the sensor chip.

3. (canceled)

9. A method for manufacturing a semiconductor chip arrangement, the method comprising

fitting an ASIC chip on a carrier by means of an adhesion layer,

providing an ASIC connection for externally electrically connecting a circuit integrated in the ASIC chip,

arranging a sensor chip above a top side of the ASIC chip, said top side facing away from the carrier, and is permanently connected to the ASIC chip, and

producing an electrical connection between the sensor chip and the ASIC chip.

10. The method as claimed in claim 9, wherein

the electrical connection between the sensor chip and the ASIC chip is produced by means of solder balls.

11. The method as claimed in claim 9, wherein

the electrical connection between the sensor chip and the ASIC chip is produced by means of stud bumps.

12. The method as claimed in claim 9, further comprising

arranging the ASIC chip in a cutout in the carrier.

13. The method as claimed in claim 9, further comprising

covering the sensor chip with a decomposable covering layer and then embedded into a filling, and

removing the covering layer to an extent such that the sensor chip is separated from the filling by an interspace.

14. The method as claimed in claim 9, further comprising

applying an adhesive layer to the carrier, and

fixing the ASIC chip on the adhesive layer, such that the adhesive layer forms the adhesion layer.

15. The method as claimed in claim 9, further comprising

applying an adhesive film to the ASIC chip and

fixing the ASIC chip on the carrier by means of the film, such that the film forms the adhesion layer.