ELECTRONIC DEVICES FORMED OF TWO OR MORE SUBSTRATES CONNECTED TOGETHER, ELECTRONIC SYSTEMS COMPRISING ELECTRONIC DEVICES, AND METHODS OF FORMING ELECTRONIC DEVICES

• US 20110233774A1
• Filed: 06/07/2011
• Published: 09/29/2011
• Est. Priority Date: 03/10/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Meade, Roy E.
• Granted Patent: US 8,570,798 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: B82Y 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: G11C 11/14 using thin-film elements
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 19/0808 using magnetic domain propagation
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/112 : directly combined with via connections
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/09381 : Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component notches in edge pads H05K2201/09181
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/36 : Assembling printed circuits with other printed circuits H05K7/142 takes precedence
• CPC Class Codes: H05K 3/4697 : having cavities, e.g. for mounting components H05K3/4691 takes precedence
• CPC Class Codes: H05K 7/04 : on conductive chassis
• CPC Class Codes: Y10S 977/932 : for electronic or optoelectronic application
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base

Abstract

Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads is positioned on a surface of the first substrate and comprises a width extending over at least two of the plurality of conductive traces. A plurality of vias extends from adjacent at least some of the conductive traces to the plurality of bond pads. The second substrate is bonded to the first substrate and comprises support circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps. Memory devices and related methods of forming electronic devices and memory devices are also disclosed, as are electronic systems.

Claims

1. An electronic device, comprising:

a first substrate bearing circuitry comprising a plurality of nanoscale pitch components within the first substrate, a plurality of microscale bond pads disposed on a surface of the first substrate, at least some microscale bond pads of the plurality of microscale bond pads being disposed respectively over at least two nanoscale pitch components of the plurality of nanoscale pitch components, and at least one via extending from at least one of the plurality of microscale bond pads to at least one component of the plurality of nanoscale pitch components; and

a second substrate comprising circuitry connected to microscale bond pads of the plurality of microscale bond pads.

2. The electronic device of claim 1, wherein the circuitry of the second substrate is electrically connected to the plurality of microscale bond pads by a plurality of conductive bumps.

3. The electronic device of claim 1, wherein at least some of the plurality of nanoscale pitch components comprise conductive traces extending at least substantially parallel to each other through a portion of the first substrate.

4. The electronic device of claim 3, wherein the plurality of conductive traces comprises a plurality of magnetic shift registers including a plurality of domains and the plurality of vias comprises a plurality of magnetic tunneling junctions.

5. The electronic device of claim 4, wherein each of the plurality of nanoscale pitch components of the circuitry comprises one of the plurality of magnetic shift registers.

6. The electronic device of claim 3, wherein at least some of the nanoscale pitch components comprise memory cells and the circuitry of the second substrate comprises at least one of a charge pump, a decode and addressing circuit, a sense amplifier, and a I/O circuit.

7. The electronic device of claim 1, wherein each microscale bond pad of the plurality of microscale bond pads comprises an area of at least about 2,000 μ

m².

8. The electronic device of claim 1, wherein at least one microscale bond pad of the plurality of microscale bond pads comprises a first diode biased in a first direction interposed between an upper conductive pad and a lower conductive pad coupled to a via of the plurality of vias and a second diode biased in a second, opposing direction adjacent the first diode, interposed between the upper and lower conductive pads, and coupled to another via of the plurality of vias.

9. The electronic device of claim 1, wherein the plurality of microscale bond pads is positioned in a pattern on the surface of the first substrate and each microscale bond pad of the plurality of microscale bond pads comprises at least one shape selected from the group consisting of square, rectangular, hexagonal, and triangular.

10. An electronic device, comprising:

a first substrate bearing circuitry comprising a plurality of nanoscale pitch components within the first substrate, a plurality of microscale bond pads having a polygonal configuration disposed on a surface of the first substrate in one of a bond shift pattern and a bond raster pattern, each microscale bond pad of the plurality of microscale bond pads being disposed over at least two nanoscale pitch components of the plurality of nanoscale pitch components, and at least one via extending from at least one of the plurality of microscale bond pads to at least one component of the plurality of nanoscale pitch components; and

a second substrate bearing circuitry operably coupled to the plurality of microscale bond pads.

11. The electronic device of claim 10, wherein at least some of the plurality of nanoscale pitch components of the circuitry of the first substrate comprise conductive traces extending at least substantially parallel to each other through a portion of the first substrate.

12. The electronic device of claim 11, wherein the plurality of conductive traces comprises a plurality of magnetic shift registers including a plurality of domains and the plurality of vias comprises a plurality of magnetic tunneling junctions.

13. The electronic device of claim 12, wherein each of the plurality of nanoscale pitch components of the circuitry of the first substrate comprises one of the plurality of magnetic shift registers.

14. The electronic device of claim 11, wherein at least some of the nanoscale pitch components comprise memory cells and the circuitry of the second substrate comprises at least one of a charge pump, a decode and addressing circuit, a sense amplifier, and a I/O circuit.

15. The electronic device of claim 10, wherein each microscale bond pad of the plurality of microscale bond pads comprises an area of at least about 2,000 μ

m².

16. The electronic device of claim 10, wherein at least one microscale bond pad of the plurality of microscale bond pads comprises a first diode biased in a first direction interposed between an upper conductive pad and a lower conductive pad coupled to a via of the plurality of vias and a second diode biased in a second, opposing direction adjacent the first diode, interposed between the upper and lower conductive pads, and coupled to another via of the plurality of vias.

17. The electronic device of claim 10, wherein the plurality of polygonal microscale bond pads comprises triangular bond pads configured in ordered pairs with bases of the triangles positioned facing each other and aligned together.

18. An electronic system, comprising:

at least one processor; and

at least one memory device coupled to the processor comprising;

a first substrate comprising a plurality of nanoscale pitch magnetic tracks within the first substrate, a plurality of microscale bond pads disposed on a surface of the first substrate, each microscale bond bad of the plurality of bond pads being disposed over at least two magnetic tracks of the plurality of magnetic tracks, and at least one tunneling junction extending from at least one of the plurality of microscale bond pads to at least one magnetic track of the plurality of nanoscale pitch magnetic tracks; and

a second substrate comprising support circuitry electrically connected to the plurality of microscale bond pads.

19. The electronic system of claim 18, wherein the second substrate is electrically connected to the plurality of microscale bond pads by a plurality of conductive bumps.

20. The electronic system of claim 18, wherein each microscale bond pad of the plurality of microscale bond pads comprises an area of at least about 2,000 μ

m².

21. The electronic system of claim 18, wherein at least one microscale bond pad of the plurality of microscale bond pads comprises a first diode biased in a first direction interposed between an upper conductive pad and a lower conductive pad coupled to a tunneling junction of the plurality of tunneling junctions and a second diode biased in a second, opposing direction adjacent the first diode, interposed between the upper and lower conductive pads, and coupled to another tunneling junction of the plurality of tunneling junctions.

22. The electronic system of claim 18, wherein the plurality of microscale bond pads is positioned in a pattern on the surface of the first substrate and each microscale bond pad of the plurality of microscale bond pads comprises at least one shape selected from the group consisting of square, rectangular, hexagonal, and triangular.

23. The electronic system of claim 18, further comprising circuitry comprising a plurality of nanoscale pitch components within the first substrate comprising at least one of a charge pump, a decode and addressing circuit, a sense amplifier, and a I/O circuit.

24. A method of forming an electronic device, comprising:

forming nanoscale pitch circuitry of a first substrate at a first temperature;

forming a plurality of vias extending from at least some components of the nanoscale pitch circuitry to a surface of the first substrate; and

aligning at least some microscale bond pads of a plurality of microscale bond pads on the surface of the first substrate respectively over at least two components of the circuitry of the first substrate;

forming circuitry of a second substrate at a second, higher temperature; and

electrically connecting the circuitry of the second substrate to the plurality of microscale bond pads.

25. The method of claim 24, wherein electrically connecting the circuitry of the second substrate to the plurality of microscale bond pads comprises electrically connecting the circuitry of the second substrate to the plurality of bond pads using a plurality of conductive bumps.

26. The method of claim 24, wherein foaming the nanoscale pitch circuitry of the first substrate at the first temperature comprises forming the nanoscale pitch circuitry of the first substrate at a temperature below about 450°

C.

27. The method of claim 24, forming the circuitry of the second substrate at the second, higher temperature comprises forming the circuitry of the second substrate at a temperature below about 1,100°

C.

28. The method of claim 24, wherein forming the nanoscale pitch circuitry of the first substrate comprises forming a plurality of plurality of magnetic shift registers including a plurality of domains and wherein forming the plurality of vias comprises forming a plurality of magnetic tunneling junctions.

29. The method of claim 24, wherein aligning the plurality of microscale bond pads on the surface of the first substrate comprises disposing a plurality of microscale bond pads having an area of at least about 2,000 μ

m² on the surface of the first substrate.

30. The method of claim 24, wherein aligning the plurality of microscale bond pads on the surface of the first substrate comprises positioning the plurality of bond pads on the surface of the first substrate in a pattern comprising one of a bond raster pattern and a bond shift pattern.