FREQUENCY DIVIDER FOR GENERATING OUTPUT CLOCK SIGNAL WITH DUTY CYCLE DIFFERENT FROM DUTY CYCLE OF INPUT CLOCK SIGNAL

• US 20110234266A1
• Filed: 12/02/2010
• Published: 09/29/2011
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Tsai, Ming-Da
• Granted Patent: US 8,314,639 B2
• Time in Patent Office: Days
• US Class Current: 327/115
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 21/023 comprising pulse shaping or differentiating circuits
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 23/425 using bistables
• CPC Class Codes: H03K 3/356173 with synchronous operation

Abstract

A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle.

Claims

1. A frequency divider, comprising:

a plurality of logic circuit blocks, each comprising a plurality of control terminals;

wherein at least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle, at least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback, and a clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle.

2. The frequency divider of claim 1, wherein the logic circuit blocks comprise a first logic circuit block, a second logic circuit block, a third logic circuit block and a fourth logic circuit block, each comprising:

a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal; and

a plurality of second transistors coupled in series between a second reference voltage and the output terminal.

3. The frequency divider of claim 2, wherein a control terminal of one of the second transistors and a connection terminal of the other of the second transistors in the first logic circuit block are cross-coupled to a connection terminal of one of the second transistors and a control terminal of the other of the second transistors in the second logic circuit block by the positive feedback.

4. The frequency divider of claim 3, wherein a control terminal of the other of the second transistors in the first logic circuit block is arranged to receive the input clock signal or a clock signal having the second duty cycle.

5. The frequency divider of claim 3, wherein a control terminal and a connection terminal of one of the first transistors in the first logic circuit block are cross-coupled to a connection terminal and a control terminal of one of the first transistors in the second logic circuit block, and a control terminal of the other of the first transistors in the first logic circuit block is arranged to receive the input clock signal or a clock signal having the second duty cycle.

6. The frequency divider of claim 3, wherein a control terminal of one of the first transistors in the first logic circuit block is arranged to receive the input clock signal, and a control terminal of the other of the first transistors in the first logic circuit block is arranged to receive a clock signal having the second duty cycle.

7. The frequency divider of claim 2, wherein a control terminal and a connection terminal of one of the second transistors in the first logic circuit block are cross-coupled to a connection terminal and a control terminal of one of the second transistors in the second logic circuit block by the positive feedback.

8. The frequency divider of claim 7, wherein another connection terminal of the one of the second transistors in the first logic circuit block is coupled to another connection terminal of the one of the second transistors in the second logic circuit block.

9. The frequency divider of claim 7, wherein a control terminal of the other of the second transistors in the first logic circuit block is arranged to receive the input clock signal.

10. The frequency divider of claim 7, wherein a control terminal and a connection terminal of one of the first transistors in the first logic circuit block are cross-coupled to a connection terminal and a control terminal of one of the first transistors in the second logic circuit block, and a control terminal of the other of the first transistors in the first logic circuit block is arranged to receive a clock signal having the second duty cycle.

11. The frequency divider of claim 7, wherein a control terminal of one of the first transistors in the first logic circuit block is arranged to receive the input clock signal, and a control terminal of the other of the first transistors in the first logic circuit block is arranged to receive a clock signal having the second duty cycle.

12. The frequency divider of claim 2, wherein a control terminal and a connection terminal of one of the first transistors in the first logic circuit block are cross-coupled to a connection terminal and a control terminal of one of the first transistors in the second logic circuit block.

13. The frequency divider of claim 12, wherein a control terminal of the other of the first transistors in the first logic circuit block is arranged to receive the input clock signal or a clock signal having the second duty cycle.

14. The frequency divider of claim 12, wherein a control terminal of one of the second transistors in the first logic circuit block is arranged to receive the input clock signal, and a control terminal of the other of the second transistors in the first logic circuit block is arranged to receive a clock signal having the second duty cycle and is not cross-coupled to any transistor in the second logic circuit block.

15. The frequency divider of claim 2, wherein the first reference voltage is higher than the second reference voltage.

16. The frequency divider of claim 2, wherein the first reference voltage is lower than the second reference voltage.

17. The frequency divider of claim 1, wherein the second duty cycle is substantially 25% or 75%, and the first duty cycle is substantially 50%.