SAMPLE AND HOLD CAPACITANCE TO DIGITAL CONVERTER

• US 20110234528A1
• Filed: 03/26/2010
• Published: 09/29/2011
• Est. Priority Date: 03/26/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Asia Pacific Pte Limited (STMicroelectronics NV)
• Inventors: Guedon, Yannick, Tan, Kien Beng
• Granted Patent: US 9,019,229 B2
• Time in Patent Office: Days
• US Class Current: 345/174
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: H03K 2217/960725 Charge-transfer
• CPC Class Codes: H03M 11/20 Dynamic coding, i.e. by key scanning H03M11/26 takes precedence
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one

Abstract

A circuit for converting charge measured from a touch screen into a digital signal can include a sample and hold circuit. The sample and hold circuit can sample and integrate a charge from a capacitive sense matrix, and hold a voltage signal representing the measured charge. A sigma delta converter can convert the voltage into a digital value.

Claims

1. A circuit for converting a measured charge into a digital signal, the circuit comprising:

a sample and hold circuit configured to sample a charge from a capacitive sense matrix and hold a signal representing the charge for a first period of time; and

an analog to digital converter that converts the signal into a digital value during the first period of time.

2. The circuit of claim 1, wherein the sample and hold circuit comprises an integrator that converts the charge into a voltage and holds the voltage for the first period of time.

3. The circuit of claim 2, wherein the hold circuit comprises a capacitor having a capacitance value that is a same order of magnitude as a capacitance between one or more selected lines and one or more selected columns of the capacitive sense matrix.

4. The circuit of claim 3, further comprising an operational amplifier having the capacitor connected between a first input terminal and an output terminal of the operational amplifier during the first period.

5. The circuit of claim 1, wherein the sample and hold circuit comprises an adjustable capacitor circuit.

6. The circuit of claim 1, wherein the analog to digital converter comprises a sigma delta converter that converts the signal into the digital value during the first period of time.

7. The circuit of claim 6, wherein the sigma delta converter is isolated from the capacitive sense matrix for the first period of time.

8. The circuit of claim 1, further comprising at least one switch that resets a voltage across a capacitance between one or more selected lines and one or more selected columns of the capacitive sense matrix during the first period of time.

9. The circuit of claim 1, wherein the capacitive sense matrix senses touch and/or proximity to a display screen.

10. The circuit of claim 9, wherein the circuit is configured such that the sample and hold circuit samples the charge during a period in which a reference voltage of the display screen is substantially constant, wherein the reference voltage creates a noise signal in the capacitive sense matrix when the reference voltage changes values.

11. A method of measuring and converting a charge into a digital signal, the method comprising:

sampling the charge from a capacitive sense matrix;

integrating the charge to produce a voltage;

storing the voltage for a first period of time; and

converting the voltage into a digital value during the first period of time.

12. The method of claim 11, further comprising:

resetting a voltage across a capacitance between one or more selected lines and one or more selected columns of the capacitive sense matrix during the first period of time.

13. The method of claim 11, wherein the sampling of the charge comprises setting the one or more selected columns to a first voltage and coupling the one or more selected lines to a readout circuit.

14. The method of claim 13, wherein the voltage is converted into a digital value using a sigma delta converter, and the method further comprises:

isolating the sigma delta converter from the capacitive sense matrix for the first period of time.

15. The method of claim 11, wherein the capacitive sense matrix senses touch and/or proximity to a display screen.

16. The method of claim 15, wherein the sampling of the charge is performed during a period in which a reference voltage of the display screen is substantially constant, wherein the reference voltage creates a noise signal in the capacitive sense matrix when the reference voltage changes values.

17. The method of claim 11, further comprising resetting a capacitor that stores the voltage.

18. The method of claim 17, wherein the capacitor is reset by turning on a switch in parallel with the capacitor.

19. The method of claim 11, further comprising:

changing a capacitance value of a capacitive circuit that stores the voltage.

20. The method of claim 19, wherein the capacitive sense matrix senses touch and proximity to a touch screen, and the method further comprises:

increasing the capacitance value to detect an object in the proximity of the touch screen; and

decreasing the capacitance value to detect an object touching the touch screen.