CAPACITANCE MEASUREMENT SYSTEM AND METHOD

• US 20110234534A1
• Filed: 06/02/2011
• Published: 09/29/2011
• Est. Priority Date: 03/16/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cormier, Ronald F. JR., Mueck, Michael
• Granted Patent: US 8,368,409 B2
• Time in Patent Office: Days
• US Class Current: 345/174
• CPC Class Codes: G01D 1/00 Measuring arrangements giving results other than momentary value of variable, of general application G01D3/00 takes precedence; in tariff metering apparatus G01D4/00; transducers not specially adapted for a specific variable G01D5/00
• CPC Class Codes: G01D 15/00 Component parts of recorders for measuring arrangements not specially adapted for a specific variable
• CPC Class Codes: G01D 21/00 Measuring or testing not otherwise provided for
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A capacitance measurement system precharges first terminals (21-0 . . . 21-k . . . 21-n) of a plurality of capacitors (25-0 . . . 25-k . . . 25), respectively, of a CDAC (capacitor digital-to-analog converter) (23) included in a SAR (successive approximation register) converter (17) to a first voltage (V_DD) and pre-charges a first terminal (3-j) of a capacitor (C_SENj) to a second voltage (GND). The first terminals are coupled to the first terminal of the capacitor to redistribute charges therebetween so as to generate a first voltage on the first terminals and the first terminal of the capacitor, the first voltage being representative of a capacitance of the first capacitor (C_SENj). A SAR converter converts the first voltage to a digital representation (DATA) of the capacitor. The capacitance can be a touch screen capacitance.

Claims

1. An apparatus comprising:

a capacitive touch screen panel; and

a successive approximation register (SAR) analog-to-digital converter (ADC) having;

a first switching circuit that is coupled to the capacitive touch screen panel;

a capacitor bank that is coupled to the switching circuit, wherein the capacitor bank includes a plurality of weighted capacitors that are coupled in parallel with one another between the switching circuit and a node;

a comparator that is coupled to the node;

SAR logic that is coupled to the comparator; and

a second switching circuit that is coupled to the first switching circuit and that is controlled by the SAR logic.

2. The apparatus of claim 1, wherein the node further comprises a first node, and wherein the capacitive touch screen panel further comprises a plurality of sensing capacitors that are arranged in an array having a plurality of rows and a plurality of columns, wherein each column is associated with at least one of a plurality of second nodes, and wherein each sensing capacitor for each column is coupled to its associated second node.

3. The apparatus of claim 2, wherein the first switching circuit further comprises:

a plurality of first switches, wherein each first switch is coupled between at least one of the second nodes and a third node; and

a plurality of second switches, wherein each second switch is coupled between the third node and at least one of the plurality of weighted capacitors.

4. The apparatus of claim 3, wherein the SAR ADC further comprises a charge pump that is coupled to the third node.

5. An apparatus comprising:

a capacitive touch screen panel having;

a first column of sensing capacitors that are each coupled to a first node; and

a second column of sensing capacitors that are each coupled to a second node;

and

a SAR ADC having;

a first switching circuit that is coupled to the first and second nodes;

a capacitor bank that is coupled to the switching circuit, wherein the capacitor bank includes a plurality of weighted capacitors that are coupled in parallel with one another between the switching circuit and a third node;

a comparator that is coupled to the third node;

SAR logic that is coupled to the comparator; and

a second switching circuit that is coupled to the first switching circuit and that is controlled by the SAR logic.

6. The apparatus of claim 5, wherein the first switching circuit further comprises:

a first switch that is coupled between the first node and a fourth node;

a second switch that is coupled between the second node and the fourth node; and

a plurality of third switches, wherein each second third switch is coupled between the fourth node and at least one of the plurality of weighted capacitors.

7. The apparatus of claim 6, wherein the first switching circuit further comprises:

a fourth switch that is coupled between the first node and ground; and

a fifth switch that is coupled between the second node and ground.

8. The apparatus of claim 7, wherein the SAR ADC further comprises a charge pump that is coupled to the third node.