CONDUCTIVE BUS STRUCTURE FOR INTERFEROMETRIC MODULATOR ARRAY

• US 20110234603A1
• Filed: 06/07/2011
• Published: 09/29/2011
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Chui, Clarence, Sampsell, Jeffrey B.
• Granted Patent: US 8,390,547 B2
• Time in Patent Office: Days
• US Class Current: 345/501
• CPC Class Codes: B81B 3/0086 Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: G09G 3/3466 based on interferometric effect
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

Embodiments of an interferometric modulator are disclosed having various enhancements and features including a conductive bus. In certain embodiments, the interferometric modulator has a first conductive layer suspended over a second electrode layer. In certain embodiments, a second conductive layer is provided over the first conductive layer. One of the first and/or second conductive buses may further connect to the first electrode layer and/or the second electrode layer. Other disclosed features can be incorporated into embodiments of the interferometric modulator to improve response time, power consumption, and image resolution.

Claims

1. An electromechanical device comprising:

an array of structures, each structure including;

a first electrode layer, and

a movable layer including a second electrode layer and a reflective surface, the movable layer being deformable in a direction towards the first electrode layer in response to a voltage applied across the first electrode layer and the second electrode layer,

wherein the first electrode layers of the array are electrically connected in series in a first direction, and

wherein the second electrode layers of the array are electrically connected in series in a second direction; and

a conductive bus structure electrically connected to either

the first electrode layers in parallel with the electrical connections between the first electrode layers in the first direction, or

the second electrode layers in parallel with the electrical connections between the second electrode layers in the second direction.

2. The device of claim 1, wherein the first electrode layers form rows in the first direction and the second electrode layers form columns in the second direction.

3. The device of claim 1, wherein the first electrode layers form columns in the first direction and the second electrode layers form rows in the second direction.

4. The device of claim 1, wherein the first electrode layers of the array are electrically isolated from one another in the second direction and the second electrode layers of the array are electrically isolated from one another in the first direction.

5. The device of claim 1, wherein the structures include interferometric modulators.

6. The device of claim 5, wherein each structure further includes an optical stack, and the optical stack includes the first electrode layer.

7. The device of claim 1, wherein the conductive bus layer has a thickness between 0.1 micron and 2 microns.

8. The device of claim 1, wherein the conductive bus layer has a width between 4 microns and 10 microns.

9. The device of claim 1, wherein the first electrode layer has a thickness between 300 angstroms and 2,000 angstroms.

10. The device of claim 1, further comprising:

a display;

a processor configured to communicate with said display, said processor being configured to process image data; and

a memory device configured to communicate with said processor.

11. The device of claim 10, further comprising:

a driver circuit configured to send at least one signal to the display; and

a controller configured to send at least a portion of the image data to the driver circuit.

12. The device of claim 10, further comprising an image source module configured to send said image data to said processor.

13. The device of claim 12, wherein the image source module comprises at least one of a receiver, transceiver, and transmitter.

14. The device of claim 10, further comprising an input device configured to receive input data and to communicate said input data to said processor.

15. A method of manufacturing an electromechanical device, the method comprising:

forming an array of structures, each structure including;

a first electrode layer, and

a movable layer including a second electrode layer and a reflective surface, the movable layer being deformable in a direction towards the first electrode layer in response to a voltage applied across the first electrode layer and the second electrode layer,

wherein the first electrode layers of the array are electrically connected in series in a first direction, and

wherein the second electrode layers of the array are electrically connected in series in a second direction; and

electrically connecting a conductive bus structure to either

the first electrode layers in parallel with the electrical connections between the first electrode layers in the first direction, or

the second electrode layers in parallel with the electrical connections between the second electrode layers in the second direction.

16. The method of claim 15, wherein the first electrode layers of the array are electrically isolated from one another in the second direction and the second electrode layers of the array are electrically isolated from one another in the first direction.

17. The method of claim 15, wherein the structures include interferometric modulators.

18. The method of claim 15, further comprising forming an optical stack, the optical stack including the first electrode layer.

19. The method of claim 15, wherein the conductive bus layer has a thickness between 0.1 micron and 2 microns.

20. The method of claim 15, wherein the conductive bus layer has a width between 4 microns and 10 microns.