NAND FLASH MEMORY

• US 20110235417A1
• Filed: 06/07/2011
• Published: 09/29/2011
• Est. Priority Date: 08/16/2006
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Isobe, Katsuaki
• Application Number:
  US13/154,522
• Publication Number:
  US 20110235417A1
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state.

Claims

1. A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, comprising

a memory cell array having a plurality of blocks each including a plurality of memory cell units, each of the memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and disposed on a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at a first gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at a second gate thereof;

wherein a first bit line that is selected is charged to a first potential while the p-type semiconductor substrate is being set at a ground potential, and the source lines, the n-type wells, the p-type wells, and a second bit line that is not selected are being charged to a second potential that is between said first potential and said ground potential at the same time as the select bit line is charged.

2. The NAND flash memory according to claim 1, wherein

a third potential equal to or lower than thresholds of the drain-side select gate transistor and the source-side select gate transistor is applied to the drain-side select gate line and the source-side select gate line of a block that is not selected.

3. The NAND flash memory according to claim 1, wherein

a third potential is applied to the word lines of said block that is not selected.

4. The NAND flash memory according to claim 3, wherein

a fourth potential is applied to the word lines of said block that is not selected.

5. The NAND flash memory according to claim 1, further comprising,

a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of the memory cell array, and applies signal voltages to word lines, the drain-side select gate lines and the source-side gate line of the memory cell array for selecting the blocks;

and

a sense amplifier that is connected to the bit lines of the memory cell array.

6. The NAND flash memory according to claim 5, wherein the sense amplifier includes:

a first transistor having a first end connected to the first bit line; and

a second transistor having a first end connected to the second bit line, a second end of the first transistor being connected to a second end of the second transistor.

7. The NAND flash memory according to claim 1, wherein the first bit line is adjacent to the second bit line.

8. The NAND flash memory according to claim 6, wherein the first bit line is selected by the first transistor turning on, and the second bit line is not selected by the second transistor turning off.

9. The NAND flash memory according to claim 1, further comprising transistors respectively having a first end and a second end, the first ends of the transistors connected to the source lines, the n-type wells, and the p-type wells respectively, and the second ends of the transistors connected with each other.

10. The NAND flash memory according to claim 9, wherein the second ends of the transistors are connected to a voltage generating circuit.

11. The NAND flash memory according to claim 6, wherein

the second end of the first transistor and the second end of the second transistor are connected to a power supply voltage.