SEMICONDUCTOR CHIP USED FOR EVALUATION, EVALUATION SYSTEM, AND REPAIRING METHOD THEREOF

• US 20110237001A1
• Filed: 02/24/2011
• Published: 09/29/2011
• Est. Priority Date: 02/25/2010
• Status: Abandoned Application

• Current Assignee: Hitachi Chemical Company Limited (Resonac Holdings Corp.)
• Original Assignee: Hitachi Chemical Company Limited (Resonac Holdings Corp.)
• Inventors: Yamamoto, Rei, Nishiki, Masashi, HASEBE, Takehiko, Temmei, Hiroyuki, Yamaguchi, Yoshihide, Kato, Masako, Inada, Teiichi, Matsushima, Naoki, Ikeda, Ukyo
• Application Number:
  US13/034,510
• Publication Number:
  US 20110237001A1
• Time in Patent Office: Days
• US Class Current: 438/4
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A technique for evaluating a semiconductor chip is provided. The semiconductor chip is mounted on a mount substrate, the semiconductor chip laminating on one surface of a silicone substrate, at least any of a metal wiring film 101 serving as a resistance temperature detector made up of multiple regions and a metal wiring film 102 serving as a heater made up of one or more regions, and an electrode 103 for connecting the metal wiring film 101 and the metal wiring film 102 with the mount substrate. Then, the metal wiring film 101 is electrically connected with an ammeter and a voltmeter, and the metal wiring film 102 is electrically connected with a power source, thereby providing an evaluation system which is capable of evaluating temperature measurement, heating, and temperature profile in each of the regions on the semiconductor chip.

Claims

1. An evaluation system for evaluating a semiconductor chip, comprising,

the semiconductor chip having on one surface of a semiconductor substrate, at least any of a first wiring film serving as a resistance temperature detector made up of multiple regions, and a second wiring film serving as a heater made up of one or more regions, and an electrode for electrically connecting the first wiring film and the second wiring film,

a mount substrate for mounting the semiconductor chip, and a thermally conductive material fixed on the mount substrate, on the other surface of the semiconductor substrate, wherein,

the first wiring film is electrically connected to an ammeter and a voltmeter, enabling measurement of temperature of each region, and

the second wiring film is electrically connected to a power source, enabling being heated of each region.

2. The evaluation system according to claim 1, wherein,

the first wiring film and the second wiring film are formed in an identical plane on the semiconductor substrate.

3. The evaluation system according to claim 1, wherein,

the first wiring film and the second wiring film are laminated, placing an insulation layer therebetween.

4. The evaluation system according to claim 1, wherein,

the first wiring film is platinum wiring film.

5. The evaluation system according to claim 1, wherein,

the second wiring film is nickel wiring film.

6. The evaluation system according to claim 1, wherein,

the second wiring film is further electrically connected to the ammeter and the voltmeter, thereby allowing the second wiring film to function as both the heater and the resistance temperature detector.

7. The evaluation system according to claim 1, further comprising,

a temperature measurement means for measuring temperature of the thermally conductive material.

8. The evaluation system according to claim 1, wherein,

the thermally conductive material is fixed on the mount substrate.

20. A repairing method for repairing the evaluation system according to claim 1, executing,

a step for heating either of the first wiring film and the second wiring film to melt a fixing material on the mount substrate,

a step for removing a device chip from the mount substrate,

a step for repairing the device chip being removed, and

a step for mounting the device chip on the mount substrate again.

9. A semiconductor chip used for evaluation, comprising a semiconductor substrate, and further comprising on a plane of the semiconductor substrate,

an insulation layer,

multiple first wiring film serving as a resistance temperature detector, made up of multiple regions,

one or more second wiring film serving as a heater, made up of one or more regions,

a first electrode electrically connected to the first wiring film, and

a second electrode electrically connected to the second wiring film.

10. The semiconductor chip used for evaluation according to claim 9, wherein,

the first wiring film and the second wiring film are laminated placing the insulation layer therebetween.

11. The semiconductor chip used for evaluation according to claim 10, wherein,

the first wiring film is provided closer to the semiconductor substrate side than the second wiring film.

12. The semiconductor chip used for evaluation according to claim 10, wherein,

the second wiring film is provided closer to the semiconductor substrate side than the first wiring film.

13. The semiconductor chip used for evaluation according to claim 10, wherein,

the number of the regions of the first wiring film is larger than the number of the regions of the second wiring film.

14. The semiconductor chip used for evaluation according to claim 10, wherein,

the region for placing one second wiring film is larger than the region for placing one first wiring film.

15. The semiconductor chip used for evaluation according to claim 9, wherein,

the first wiring film and the second wiring film are arranged in an identical plane.

16. The semiconductor chip used for evaluation according to claim 9, wherein,

the first wiring film is platinum wiring film.

17. The semiconductor chip used for evaluation according to claim 9, wherein,

the second wiring film is nickel wiring film.

18. The semiconductor chip used for evaluation according to claim 9, wherein,

the first wiring film has the first electrodes used in a pair for each region, and

the second wiring film has the second electrodes used in a pair for each region.

19. The semiconductor chip used for evaluation according to claim 18, wherein,

four first electrodes are provided in one region of the first wiring film.